JPS5671145A - Information processing device - Google Patents

Information processing device

Info

Publication number
JPS5671145A
JPS5671145A JP14798079A JP14798079A JPS5671145A JP S5671145 A JPS5671145 A JP S5671145A JP 14798079 A JP14798079 A JP 14798079A JP 14798079 A JP14798079 A JP 14798079A JP S5671145 A JPS5671145 A JP S5671145A
Authority
JP
Japan
Prior art keywords
correction
address
control memory
error
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14798079A
Other languages
Japanese (ja)
Inventor
Toshinori Ishigaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14798079A priority Critical patent/JPS5671145A/en
Publication of JPS5671145A publication Critical patent/JPS5671145A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to correct micro instructions and execute the program again without sacrifice of the processing speed for troubles in the control memory, by giving a constitution where error detection and correction based on the check bit are performed only for occurrence of parity errors.
CONSTITUTION: The micro instruction read from control memory part 11 according to the address set into micro address counter 12 is checked for parity by parity check circuit 13. If an error is detected, the interrupt signal is applied to the operation processing part through NAND gate 14, and the start address of the microprogram (MP) for error correction stored in the control memory part is set to counter 12, and the control is brancked to MP for correction, and the check bit stored in the control memory part is used to correct the error in the operation processing part. When agreement between the address for the correction micro instruction held in address register 16 and contents of counter 12 is detected by comparing circuit 17, the correction micro instruction held in data register 15 is taken out by selector 18 selectively.
COPYRIGHT: (C)1981,JPO&Japio
JP14798079A 1979-11-15 1979-11-15 Information processing device Pending JPS5671145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14798079A JPS5671145A (en) 1979-11-15 1979-11-15 Information processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14798079A JPS5671145A (en) 1979-11-15 1979-11-15 Information processing device

Publications (1)

Publication Number Publication Date
JPS5671145A true JPS5671145A (en) 1981-06-13

Family

ID=15442441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14798079A Pending JPS5671145A (en) 1979-11-15 1979-11-15 Information processing device

Country Status (1)

Country Link
JP (1) JPS5671145A (en)

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