JPS5619129A - Input and output control unit having spare processor - Google Patents

Input and output control unit having spare processor

Info

Publication number
JPS5619129A
JPS5619129A JP9437779A JP9437779A JPS5619129A JP S5619129 A JPS5619129 A JP S5619129A JP 9437779 A JP9437779 A JP 9437779A JP 9437779 A JP9437779 A JP 9437779A JP S5619129 A JPS5619129 A JP S5619129A
Authority
JP
Japan
Prior art keywords
failure
hardware
input
delivered
instruction execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9437779A
Other languages
Japanese (ja)
Other versions
JPS6112585B2 (en
Inventor
Norihiko Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9437779A priority Critical patent/JPS5619129A/en
Publication of JPS5619129A publication Critical patent/JPS5619129A/en
Publication of JPS6112585B2 publication Critical patent/JPS6112585B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To increase the reliability of system, by providing the spare processor to the input and output unit, storing the program required at failure in the control storage section, and reporting the failure taken place in the hardware of the main processor to the upper rank unit.
CONSTITUTION: When a hardware failure is taken place at the main processor, the hardware error detector 14 detects the failure and the detection signal is delivered to the instruction execution section 8' of the spare processor and the control signal is delivered to the instruction execution section 8 to tentatively stop the control operation of the main processor. Further, the control signal from the detector 14 is delivered to the error display register 15 to display the status of the hardware failure. Further, the instruction execution section 8' reads out the microprogram at the failure stored in advance from the memory 6' and the failure status of the register 15 and the program are input to the special register 12 to execute the failure processing by taking the operation circuit 7' as a center and the failure information is transmitted to the upper rank unit via the channel interface control circuit 13.
COPYRIGHT: (C)1981,JPO&Japio
JP9437779A 1979-07-24 1979-07-24 Input and output control unit having spare processor Granted JPS5619129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9437779A JPS5619129A (en) 1979-07-24 1979-07-24 Input and output control unit having spare processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9437779A JPS5619129A (en) 1979-07-24 1979-07-24 Input and output control unit having spare processor

Publications (2)

Publication Number Publication Date
JPS5619129A true JPS5619129A (en) 1981-02-23
JPS6112585B2 JPS6112585B2 (en) 1986-04-09

Family

ID=14108620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9437779A Granted JPS5619129A (en) 1979-07-24 1979-07-24 Input and output control unit having spare processor

Country Status (1)

Country Link
JP (1) JPS5619129A (en)

Also Published As

Publication number Publication date
JPS6112585B2 (en) 1986-04-09

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