JP2503980B2 - Memory diagnostic circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory diagnostic circuit suitable for diagnosing a read-only memory in an information processing device, particularly a read-only memory of a microprogram controller.

2. Description of the Related Art In a microprogram controller, a method called checksum is known as one method for diagnosing this read-only memory.

That is, the microprogram stored in the read-only memory is read out as data one word at a time and is successively operated, and it is checked whether or not the final operation value becomes a predetermined value.

Problems to be Solved by the Invention In the above-described conventional diagnosis method, if an abnormality occurs in a portion of a microprogram that executes the diagnosis of the read-only memory, the diagnosis cannot be performed correctly even if there is no abnormality in other portions. There's a problem.

In addition, since the microprogram includes a diagnostic portion, there is a problem that the capacity of the read-only memory increases accordingly.

Configuration of the Invention Means for Solving Problems The memory diagnostic circuit of the present invention which solves the problems of the above-mentioned prior art provides an address from its minimum address to its maximum address to a read-only memory when a reset signal is input. Maximum address detection means for detecting that the sequentially generated address counter has generated the maximum address, and a diagnostic mode selection command when the reset signal is input, and after the maximum address detection means detects the maximum address. Is used as a mode switching means for instructing selection of the normal mode instead of the diagnostic mode, as a register for storing the operation result in the diagnostic mode, and as an instruction register for holding the instruction read from the read-only memory in the normal mode, Moreover, the initial state is cleared by the input of the reset signal. When the buffer register and the mode switching means are instructing the selection of the diagnostic mode, one word of parallel data output by the read-only memory and the data held by the buffer register are operated to be stored in the buffer register. When the mode switching means commands the selection of the normal mode, the arithmetic means for holding parallel data of one word output from the read-only memory in the buffer register as it is, and the maximum address detecting means. A diagnostic means for verifying the data held in the buffer register when the maximum address is detected, and the diagnostic portion of the conventional microprogram is replaced by the addition of a minimum amount of hardware, thereby diagnosing the microprogram. Is configured to be unnecessary.

 Hereinafter, the operation of the present invention will be described in detail with reference to Examples.

First Embodiment FIG. 1 shows the configuration of a memory diagnostic circuit 1 according to an embodiment of the present invention, in which a memory 21 to be diagnosed and its address counter are shown.
FIG. 23 is a block diagram showing the relationship with 22.

This memory diagnostic circuit 1 is provided with a maximum address detecting means 11,
It is provided with a mode switching means 12, a calculation means 13, a buffer register 14 and a verification means 15.

The maximum address detecting means 11 receives the address of the read-only memory 21 output from the address counter 22, and when this is the maximum address, generates a notification signal to that effect. The mode switching means 12 receives the reset signal from the outside and the notification signal from the maximum address detecting means 11 and calculates means.
The operation mode of 13 is determined, and the operation circuit 13 is instructed to select the operation mode. The hydrochloric acid means 13 has a read-only memory 21.
1-word data output from the buffer register
Upon receiving the data held by 14, the operation result of both data or the output data itself of the read-only memory 21 is held in the buffer register 14 according to the mode selection command of the mode switching means 12.

The buffer register 14 temporarily holds the calculation result of the calculation means 13 or the output data of the read-only memory 21. The verification means 15 receives the data held in the buffer register 14 and verifies whether the data held in the buffer register 14 is a predetermined value when the maximum address detection means 11 detects the maximum address.

First, the reset signal from the outside is the mode switching means 12
To the diagnostic mode, the buffer rest 14 to the initial state, and the address counter 22 to the read-only memory 21 for instructing the minimum address.

Next, as the address counter 21 sequentially increments the address, the operation means 13 causes the read-only memory 21 to read 1
The word output data and the data held in the buffer register 14 are operated, and the operation result is held in the buffer register 14. Address counter 22 is read-only memory 21
The above operation is repeated until the maximum address is designated. When the address counter 22 indicates the maximum address, the maximum address detection means 11 notifies the mode switching means 12 and the verification means 15 to that effect.

Upon receiving the notification from the maximum address detecting means 11, the verifying means 15 compares the final calculation result stored in the buffer register 14 with a predetermined internal value, and notifies the outside of this matching result. The mode switching means 12 is the maximum address detecting means 11
Detects the maximum address, it switches from diagnostic mode to normal mode. In this normal mode, the calculation means 13
Causes the buffer register 14 to hold the one-word output data output from the read-only memory 21 as it is. Therefore, in the normal mode, the buffer register 14 is used as it is as a general-purpose instruction register for temporarily holding one-word data output from the read-only memory 21 via the arithmetic means 13.

EFFECTS OF THE INVENTION As described in detail above, the memory diagnostic circuit of the present invention serves as a register for storing operation results in the diagnostic mode, and as an instruction register for holding an instruction read from the read-only memory in the normal mode. Since the arithmetic unit that doubles as one buffer register and performs the arithmetic operation in the diagnostic mode and the transfer operation in the normal mode is installed in the subsequent stage of the read-only memory,
The diagnostic part of the microprogram can be eliminated by adding a minimum amount of hardware.

As a result, a diagnostic error due to the occurrence of a failure in such a diagnostic portion is prevented and the memory capacity is reduced accordingly.

[Brief description of drawings]

FIG. 1 shows a configuration of a diagnostic circuit according to an embodiment of the present invention, in which a read-only memory 21 to be diagnosed and its address counter 22 are provided.
It is a block diagram shown with relation with. 11 …… Maximum address detection means, 12 …… Mode switching means,
13 ... Calculation means, 14 ... Buffer register, 15 ... Verification means.

Claims (1)

(57) [Claims] 1. A maximum address detecting means for detecting that an address counter, which sequentially generates an address from its minimum address to its maximum address in a read-only memory when a reset signal is input, has generated the maximum address. Mode switching means for instructing selection of a diagnostic mode when the reset signal is input, and for instructing selection of a normal mode instead of the diagnostic mode after the maximum address is detected by the maximum address detecting means, and a calculation in the diagnostic mode As a register to store the result,
A buffer register which is used as an instruction register for holding an instruction read from the read-only memory in the normal mode, and which is cleared to an initial state by the input of the reset signal, and the mode switching means instructs selection of a diagnostic mode. In this case, the parallel data of one word output from the read-only memory and the data held in the buffer register are operated and held in the buffer register, and the mode switching means commands the selection of the normal mode. The parallel data of one word output from the read-only memory is stored in the buffer register as it is, and the data stored in the buffer register when the maximum address detection unit detects the maximum address. And a verification means for verifying Li diagnostic circuit.