JPH01217655A - Diagnostic system for memory - Google Patents

Abstract

PURPOSE:To extremely shorten a diagnosing tie and to extremely decrease the quantity of diagnosis data by using the output of an address generating circuit and the diagnosis data on a write data register of a memory at diagnosis of this memory. CONSTITUTION:After the diagnosis data received from a data bus 4 is written into an existing write data register of a memory 2, the diagnosis data of the write data register is written into the memory area designated by an address every time this address is produced. Then a similar reading address is produced and the data are read out of the divided memory areas that undergo the same diagnosis. Then the read data are transferred to an address device 5 via the bus 4 with no or secured among these read data and then used for diagnosis of the memory 2. Thus it is possible to extremely shorten the diagnosing time and to extremely decrease the quantity of the diagnosis data.

Description

[Detailed Description of the Invention] [Summary] Regarding a storage device diagnostic method that detects failures by sampling the address space to be diagnosed, reliability is improved by significantly shortening diagnostic time and significantly reducing diagnostic data. In an information processing system that includes a storage device, an address bus, a data bus, and an access device that accesses the storage device via the bus, the purpose is to contribute to the generation of access addresses given via the address bus. an address generation circuit that sequentially generates access addresses to the divided storage area to be diagnosed from an access start address of the memory area; and a connection circuit that receives a diagnostic mode signal from the access device and connects the output of the address generation circuit to the storage device. The output of the address generation circuit and the diagnostic data of the write data register of the storage device are used when diagnosing the storage device.

[Industrial application field]

The present invention relates to a storage device diagnostic method for detecting failures by sampling a diagnosis target address space.

In an information processing system, the data processed therein and the programs therefor are stored in a storage device. Even if such a storage device does not have a fault during its manufacture, a part of it may develop a fault after it is used. Since such a failure makes it impossible to continue normal data processing, it is necessary to check for the presence of the above-mentioned failure when the system is in operation.

The capacity of the above-mentioned storage devices has been increasing due to the performance and purpose of the system, user requirements for the system, and advances in integrated circuit technology. This causes the above-mentioned check to take a long time to execute the diagnosis, resulting in a decrease in reliability in the operation of the information processing system.

[Conventional technology]

In conventional systems, storage device diagnostic methods sequentially diagnose all storage areas of the storage device to be diagnosed under the control of a central processing unit that executes a diagnostic program.

That is, diagnostic data is written in these storage areas and read out to check whether a failure has occurred in that storage area.

[Problem to be solved by the invention]

In this conventional method, since the diagnosis process is performed sequentially on all storage areas to be diagnosed, the time required for diagnosing the storage device is unavoidably long. For example, if the address and data fetch time for diagnosis of a storage device having a storage capacity from address 0 to α is TF, and the write time and read time of the storage device are Tw and TR, respectively, then the storage device The time T0 required for diagnosis is To””
'(Ty +7w)Xα+(TF +T*)xα=
(2TF+Tw+Ti)Xα ・ ・ ・(
1).

In addition, this diagnostic time tends to become longer due to the increase in storage capacity as mentioned above, and this has become a problem that must be solved in order to maintain the reliability of the system.
There is no choice but to increase the amount of data needed for diagnosis.

The present invention was created in view of such technical problems, and provides a storage device diagnostic method that contributes to improving reliability by significantly shortening diagnostic time and diagnostic data. Its purpose is to

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention.

As shown in this figure, the present invention provides an information processing system that includes a storage device 2, an address bus 3, a data bus 4, and an access device 5 that accesses the storage device 2 via the bus 3.4. , an address generation circuit 8 that sequentially generates an access address for the divided storage area to be diagnosed from an access start address for generating an access address given via the address bus 3; and a diagnostic mode signal received from the access device 5. and a connection circuit 10 for connecting the output of the address generation circuit 8 to the storage device 2, and when diagnosing the storage device 2,
The memory device 2 is configured to be diagnosed using the output of the address generation circuit 8 and diagnostic data of the write data register of the memory device 2.

[For production]

In the diagnostic mode of the storage device of the information processing system, a diagnostic mode signal is applied from the access device 5 to the connection circuit IO. As a result, the address generation circuit 8
connected to. The address generation circuit 8 has been given an access start address by the time of the connection, and sequentially generates access addresses for the divided storage area to be diagnosed from the access start address. This sequential address causes an access to the divided storage area to be diagnosed in the storage device 2. That is, after the diagnostic data from the bus 4 is written to the existing write data register in the storage device 2, each time the above-mentioned address is generated, the diagnostic data of the write data register is written to the storage area specified by that address. Data is written. After that, a similar read address is generated to read data from the same divided storage area to be diagnosed, and each successive data is not logically summed and the read data is The data is transferred to the address device 5 via the bus 4 and used for diagnosing the storage device 2.

〔Example〕

FIG. 2 shows an embodiment of the invention. This figure representatively shows each component of each prefecture, such as an information processing system, such as a switch with a duplex configuration, where 2 is a storage device, 3 is an address bus, and 4 is a data bus. These buses are connected to a central control unit (hereinafter simply referred to as CC) (not shown) of the exchange. Address bus 3 is directly connected to an address driver (not shown) of storage device 2 via switching circuit 101 for normal storage device access.

The switching circuit 10+ causes a direct connection of the address bus 3 to the storage device 2 when the flip-flop circuit 10□ is off, and connects the output of the address generation circuit 8 to the storage device 2 when the flip-flop circuit 102 is on. bring about. The flip-flop circuit 10□ is switched by an on/off control signal applied via a control line 9 from a central controller.

Switching circuit 10. and the flip-flop circuit 102 is the first
This is an example of the connection circuit 10 shown in the figure.

The data bus 4 is the write data register 12 of the storage device 2.
to its write input via.

The read output of the storage device 2 is often connected to the read data storage circuit 18 or the output circuit 20 via the switching circuit 14. The connection of the continuous output by this switching circuit 14 to the read data storage circuit 18 is a flip-flop circuit (FF
) 16 is on, and the connection of the readout output to the output circuit 20 is caused when the flip-flop circuit (FF) 16 is off. The output circuit 20 is, for example, a known parity/ECC check circuit.

As shown in FIG. 6. Delay circuit to prevent it from being changed. be configured as necessary. Adder circuit Eel is storage buffer 6
This is for updating the address of , by a predetermined address increment value (β).

Further, the read data storage circuit 18 includes a buffer 1B3.184, an OR circuit 182, and a storage buffer 183, as shown in FIG.

The diagnostic operation of the storage device in such a system configuration will be described below.

Access to the storage device 2 during normal system operation is as follows. That is, in this case, the flip-flop circuits 10g and 16 are off, and the address bus 3 is directly connected to the address drive section of the storage device 2. As a result, from CC to address bus 3, switching circuit 1
An access to the storage device 2' is caused by an address applied to the storage device 2 via 0+. If the access is for writing, the write data is set in the write data register 12 of the storage device 2 via the data bus 4, and then the memory cell section (
(not shown). Also, for reading, CC
The data read from the storage device 2 set in the read mode is transferred to the CC via the switching circuit 14, the output circuit 20, and the data bus 4.

When the system enters diagnostic mode for storage device 2, C
Flip-flop circuit 10. ．． 16 is set. Further, the access mode of the storage device 2 is set to write mode under the control of the CC.

With this setting, each address sequentially generated from the address generation circuit 8 is transferred to the switching circuit 10. is applied to the address driver of the storage device 2 via the address driver.

The address generation circuit 8 sequentially generates addresses as follows. After the start address for sequential address generation is stored in the accumulation buffer 6I from CC at a predetermined timing TA, the start address is stored in the delay circuit 64 provided as necessary, then in the accumulation buffer 6□, and then T
At the timing when A/N=TB (access timing of the storage device 2), β (address update value, that is, the value for dividing the memory cell area of the storage device 2 into N) to the value of the storage buffer 6□. Addition is performed by an adder circuit 63, and each addition causes the contents of the accumulation buffer 6□ to be updated with the updated value. This sequentially updated value becomes the address A2 that is sequentially generated as described above.

A group of storage areas that are accessed for writing by this sequential address A2 (the same applies to read access described later) are the divided storage areas to be diagnosed in the present application.

Along with writing the starting address for generation of such an address into the storage buffer 6I, diagnostic data is set in the write data register 12 from the CC via the data bus 4.

The diagnostic data is stored from the write data register 12 in synchronization with the addresses being sequentially generated from the address generation circuit 8 and applied to the address drive section of the storage device 2 via the switching circuit 10+ as described above. Device 2
is applied to the write input of Thus, the starting address γ mentioned above. Diagnostic data is written to the storage device 2 at address intervals of β to β as shown in FIG.

After this writing is completed, the access mode to the storage device 2 is switched to the read mode, and the read start address γ is set. is written from the CC to the storage buffer 6 via the address bus 4, resulting in the generation of sequential addresses in the same manner as described above. These sequential addresses are applied to the address driver of the storage device 2 via the switching circuit 101. As a result, the data sequentially read out from the storage device 2 is applied to the read data storage circuit 18 via the switching circuit 14 and is logically summed. That is, the upcoming read data that is sequentially sent to the read data storage circuit 18 is initially cleared in the buffer 18. and is logically ORed with the data in the buffer 184 in the OR circuit 18t. Buffer 184 is initially cleared. The output data of the OR circuit 18□ is written to the accumulation buffer 183. This accumulation buffer 183 is also initially cleared. The data in the accumulation buffer 183 is stored in the buffer 18. The data is written to the buffer 184 at the same timing as the data is written to the buffer 184. In this way, the accumulation buffer 18. The logical sum of each successive data stored in is taken into the CC via the output circuit 20 and the data bus 4 before starting diagnosis for the next divided storage area to be diagnosed.
Subjected to diagnostic checks.

If there is an abnormality in the check results, a specific address for failure detection is checked, and the printed board corresponding to the failure location is replaced to recover from the failure.

The starting address γ mentioned above. If there is no abnormality in the check result for the divided storage area to be diagnosed starting from , the same diagnosis as described above is started for the divided storage area to be diagnosed starting from the next start address TI (see FIG. 5). The following is the same as described above.

If such a storage area division diagnosis method is adopted, the diagnosis time can be significantly shortened. For example, when the fetch time TF, write time T-, and read time T, l explained in the conventional method described above are the same, the diagnosis time TN in the present invention is T, ='r,xβ+T8×(βXN)+T, Xβ10TI
I×(βXN) =T, Xβ+T w X 2 + T yβ+TIIα
=2T, β+(T w + T R) α...
・(2) becomes.

Comparing the diagnosis time in the method of the present invention and the diagnosis time in the conventional method, from the above equations (1) and (2), (
1)-(2)-2(α-β)T,>0, and according to the present invention, the diagnosis time can be shortened.

When a check error occurs, the address check to identify the fault source is α+βXi (i=
o, 1. ..., n).

If β is exactly the next storage element replacement unit (for example, a printed circuit board mounted with a memory cell storage unit), and if a failure occurs at the address of that storage element replacement unit, other memory element replacement units within the storage element replacement unit It is also possible that a failure has occurred at this address (finish the diagnosis for the next starting address,
It is thought that it would be better to enter the fault identification process to further shorten the diagnosis time), and also considering that the memory element replacement unit is usually replaced without repairing the faulty part. The method of the present invention can be said to be an extremely effective diagnostic method.

In addition, it is sufficient to prepare diagnostic data from To to γ and -3 regardless of whether they are different or different in the memory division shown in FIG.

In the above embodiment, addresses for diagnosis may be generated using a random sampling method.

Alternatively, the storage device may be composed of a single storage device. It is also possible to switch between the address supply route in normal processing and the address supply route in diagnostic processing on the input side of the address generation circuit.

〔Effect of the invention〕

As described above, according to the present invention, instead of proceeding with diagnostic processing sequentially for all address spaces of a storage device from the beginning, divided address spaces are diagnosed using a sampling method, which reduces diagnostic execution time. Not only is this achieved, but the diagnostic data is also significantly reduced. Furthermore, when adding storage capacity, the diagnostic data that was used before the capacity increase can be used to diagnose the storage device whose capacity has been increased, so there is no need to add diagnostic data as the capacity is increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram showing an address generation circuit. FIG. 4 is a diagram showing a read data storage circuit. The figure is a developed diagram of the storage address space divided. 1 and 2, 2 is a storage device, 3 is an address bus, 4 is a data bus, 5 is an access device (central control unit of the exchange), and 8 is an address generation circuit (storage buffers 61, 6□, adder). Circuit 6.
), 10 is a connection circuit (switching circuit 10+, flip-flop circuit 10□). Woman's Book, Invention (71 Principles 7 Block 7 Figure 1 OC0-J
Lノζ Address 柾circuit 3rd figure

Claims (1)

[Claims] (1) It has a storage device (2), an address bus (3), a data bus (4), and an access device (5) that accesses the storage device (2) via the buses (3, 4). In the information processing system, the address bus (3)
an address generation circuit (8) that sequentially generates an access address to the divided storage area to be diagnosed from an access start address for generating an access address given through the;
A diagnostic mode signal is received from the access device (5) and the output of the address generation circuit (8) is sent to the storage device (2).
), and when diagnosing the storage device (2), using the output of the address generation circuit (8) and diagnostic data of the write data register of the storage device (2), A diagnostic method for a storage device, characterized in that the storage device (2) is diagnosed.