JP2003337758A - Duplexed memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a computer and to facilitate error restoration, repair, and replacement during operation of a system. <P>SOLUTION: A processing device 1 and a system bus controller 3 are connected together via a CPU bus, and the system bus controller 3 and a memory device 4 are duplexed to be connected to a pair of system buses 13 individually. Inside the system bus controller 3 and the memory device 4, error detection circuits 6, 80, and 85 for detecting errors in the respective buses, comparison circuits 51, 104, and 105 comparing bus output contents, bus switch circuits 7, 82, and 83, and mode setting circuits 100, 101, and 102 are arranged. Outputs of the error detection circuits are exchanged between a pair of devices, and according to a detection result from a partner side and setting contents of the mode setting circuit, the bus switch circuit is controlled. <P>COPYRIGHT: (C)2004,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly reliable computer.
Memory device, particularly a method for configuring a redundant memory system,
The present invention relates to a diagnosis method and a failure monitoring method. [0002] In the field of fault-tolerant computers,
And one of the most common techniques to increase computer reliability
In addition, reliability such as processing unit (CPU) or storage device
There is a method of multiplexing upper critical logic circuits. Through
Usually, multiplexing of storage devices is based on duplication,
Configure one of the storage devices as the service side and the other as the standby side
You. In this case, write the same data to both
To ensure consistency, and only read the data on the regular side when reading.
Error, but data read from the regular side
Occurs, the data transfer subject switches to the standby side,
This is the system operation by outputting the correct data
Continuation becomes possible. [0003] However, in the conventional technology, most of the memory is used.
Only the equipment is duplicated, and the control unit and connected system
No reliable method has been established by duplicating the system bus.
No. Therefore, a method of diagnosing the failed storage device separately
Stage, repair replacement during system operation (hot line replacement), storage device
What to do if the system bus connecting the
Was also inadequate. [0004] As a switching technology for a redundant storage device, there is a special technique.
JP-A-59-17796, JP-A-01-70847
JP, JP-B-60-3225, JP-A-63-2
73950, JP-A-60-238957,
JP-A-57-109195, JP-A-4-2330
In the method described in Japanese Patent Publication No. 52, the connection of a storage device is performed.
Buses are not duplicated and most systems
, The control unit was not duplicated. Further
If an error occurs in the storage device at
Although correct data is guaranteed by replacement or repair,
Insufficient consideration during writing, due to retry operation, etc.
In this case, the performance is deteriorated and the circuit on the processing device side is complicated.
In addition, when diagnosing a failed memory, it affects the normal memory
System that failed control unit or memory device
The means for repair and replacement during system operation and the I / O controller are stored
Despite sufficient consideration of reliability when accessing equipment
And there is room for improvement in the overall system reliability.
Met. [0005] As described above, the prior art
Surgery has several challenges, and to solve this,
Is a method of duplicating all components.
This can be achieved simply by preparing two sets of components.
But always ensure correct continuous operation as a system
Therefore, the following points must be considered. Problem 1: Disconnection of a duplicated system bus
Replacement is fast and the system is ready when an error occurs.
Normal data without changing the bus timing.
Guarantee. [0007] Problem 2, any of the duplicated devices
Normal operation is possible even if one of the devices is not mounted,
A special signal to know if the other side is implemented
No need for highway. [0008] Problem 3: Identification of failure location when an error occurs
And diagnosis without affecting normal parts.
When. Problem 4: Data parity error during writing
Simple means to continue redundant operation even when
To provide. Problem 5, when the system bus is duplicated
Ensure that error checking is performed adequately. Problem 6, One of the duplicated memory devices
Do not shut down the system when an unrecoverable error occurs.
That can be repaired and replaced, and that redundant operation can be resumed. Problem 7, Do not use as a dual memory device
To easily increase the memory capacity at times. Problem 8, Diagnosing a failed input / output control device
Recovery by writing data to memory when
Do not cause impossible memory destruction. Problem 9, connection to a duplicated system bus
Without having to design a special input / output control
Connect to redundant memory systems without compromising reliability
Make it possible. [0015] The present invention has been made to solve the above problems.
To provide a highly reliable dual memory system
With the goal. Means for Solving the Problems To solve the above problems
In addition, the present invention provides a processing apparatus for performing various processes,
System bus connected to the device via a CPU bus
The controller and this pair of system bus controllers
And a pair of system buses connected and connected to each other.
A pair of memory devices respectively connected to the
During the write operation in the processing unit, the system bus
The control device simultaneously stores data from the processing device in a pair of memory devices.
Data during the read operation in the processor,
Memory supported by one of the system bus controllers
Redundant transmission of data read from the device to the processing device
In the memory system, each system bus control device
Data being transferred and located on the path where data is transferred
Error detection means for detecting errors
Detection means.
Error status register that holds the result of the check
According to the contents of the error status register.
Output of data read from the memory device to the CPU bus
And a CPU bus switching circuit for determining the
You. According to the present invention, the transfer error detecting means is switched.
Detects errors in the data being sent, and sets the error status
And the CPU bus switching circuit holds the detection result.
CPU bus according to the contents of the error status register.
Is determined as to whether or not to output data. [Embodiment 1] FIG. 1 shows a first embodiment of the present invention.
This is a redundant memory system. In FIG.
Processing device (CPU) 2, processing device 1 performs special processing such as diagnosis
A control ROM storing a program for performing
3 controls the exchange of the system bus with the processing device 1.
4 is a memory device, 5 is a system bus controller
The system is built in the system bus controller 3 and has a memory device during normal operation.
The data read from the device should be sent to the processing device 1.
Master determination for determining the system bus controller
The path 6 is built in the system bus controller 3 and has a memory device.
Error for detecting an error in the data read from
A detection circuit 7 is a master determination circuit and an error detection circuit 6
Whether to output read data to the processing unit according to the instruction
CPU bus switching circuit for determining whether Processing device 1
And the system bus controller 3 transmits the data signal 8 and the low level
Signal 9, high-level interrupt signal 10, address signal 1
1 connected by CPU bus
The control device 3 and the memory device 4 are duplicated,
a, 3b, 4a, and 4b. Duplex system
The stem bus control device includes a CPU bus switching signal line 12a.
And 12b, and the memory device 4a is connected to the system bus.
Memory to the system bus control device 3a via A13a.
The device 4b is connected to the system bus via the system bus B13b.
It is connected to the control device 3b. The duplicated portion is composed of the A system and the B system as described above.
However, in the following description, both sides are distinguished.
Suffix a or b to each component number.
When no distinction is made, they are indicated without subscripts. FIG. 2 shows the system bus control unit 3 shown in FIG.
Error detection circuit 6 and CPU bus switching circuit built in
The detailed configuration of the road 7 is shown. 13-1 in the figure is from the memory device
Data signal read out and sent out on the system bus
Consists of 32 bits for the data part and 4 bits for the parity part
Is done. Reference numeral 14 denotes a data signal 13-1 which is a clock signal 15
Data latch circuit that outputs the data signal 16 latched by
Path 17 latches data signal 16 with clock signal 15
A data latch circuit that outputs the data signal 18
Is an error detection that performs a parity check on the data signal 16.
Circuit 12 is the output of error detection circuit 19 when an error is detected
Error signal line which becomes "1" and CPU bus switching
Used as a signal line, 20 is the output of the error detection circuit 19
The normal signal line which becomes “1” when no error is detected
Should send read data to CPU bus when no error is detected
Master mode input signal to select system bus controller
Line 22, indicates that valid data is being transmitted from the memory device.
Data valid signal line indicating that the
Force signal line 21, data valid signal line 22, error signal line 1
2 and the state of the normal signal line 20 are determined by AND gates 24 and 25.
And the signal conditionally output by the OR gate 26 is latched.
A CPU bus selection latch. 29 is a CPU bus
Output latch 33 and data output timing
Gate signal 32 is generated according to the condition of clock signal 30
An AND gate 31 for performing a gate signal 32
When "1", the data signal 18 is the data signal of the CPU bus.
8 when the gate signal 32 is “0”.
Three-state battery that puts the
, 34 is the CPU from the other system bus controller.
With a pull-up resistor that pulls up the bus switching signal 12
is there. 35 is a CPU bus switching signal line 12a or
Is a low level ratio when one of 12b is "1".
EXOR gate for generating an embedded signal 9 and a CPU bus 36.
When both the switching signal lines 12a and 12b are "1"
AND gate that generates a high-level interrupt signal 10
is there. EXOR gate 35 and AND gate 36
And two types of interrupt signals to the processing unit are generated.
You. Error occurrence status and CPU bus switching signal line 12,
FIG. 3 shows the relationship between the interrupt signal lines 9 and 10. FIG. 4 shows the error detection circuit and the CPU shown in FIG.
FIG. 9 is a timing chart showing the operation of the bus switching circuit.
The output signals are shown correspondingly. T01 to T in the figure
14 is a clock cycle based on the clock signal 15
Is shown. FIG. 5 shows that the data signal 18 is the gate signal 32
Is driven as a data signal 8 at the timing of
It shows how it works. FIG. 6 shows the inside of the system bus controller 3 of FIG.
The details of the master determination circuit 5 of the section will be described. In the figure, 37 is the mode.
Output signal line 41 with a flip-flop
Power. 38 is a master change signal line for changing the master, 3
9 and 40 are AND gates of negative logic, 42 is at power-on
Reset the flip-flop 37 to the initial state.
Signal line. When incorporating the master decision circuit in Fig. 2
Output signal 41 instead of master mode input line 21
Connected. FIG. 7 shows the operation of the master decision circuit of FIG.
FIG. The dual memory system configured as described above
The schematic operation of the system will be described with reference to FIG. processing
The apparatus 1 performs control R
Executing the program stored in OM2, the system
After diagnosing the memory device 4 connected to the bus 13,
Via an input / output control device such as a disk control device (not shown)
To load a program such as an OS into the memory device 4,
Thereafter, while the system operates normally, the data is stored in the memory device 4.
Executes the specified program. Error detected in system
Then, an interrupt signal 9 or 10 is sent to the processing device 1.
The processing device 1 performs a predetermined error processing in the control ROM 2.
Memory device 4 after executing the error management program and completing the error processing.
Resumes execution of the program stored in. When the processing device 1 executes the program,
When accessing the storage device 4, if a write operation is performed,
Via the system bus controllers 3a and 3b
Is simultaneously written to the memory devices 4a and 4b on the
You. During the read operation, the system bus controllers 3a, 3b
Both instruct the memory device to read,
Reading is performed simultaneously from the devices 4a and 4b, and the system
Bus A 13a and 13b via the system bus control unit.
The read data is sent to the devices 3a and 3b. System bar
The master control circuit 5 is built in the
And the error detection circuit 6 is sent from the memory device.
If the data shows no error,
Sends the read data to the CPU bus data 8.
If an error is detected, the system
CPU control signal line 1
2 is output by the CPU bus switching circuit 7 to the normal side.
System bus controller reads CPU bus data 8
Send data. Next, error detection circuit 6 and CPU bus switching
The detailed operation of the circuit 7 will be described with reference to FIG. In FIG. 2, the system bus control device
There is a star mode input signal line 21.
In the control device 3a, the master mode input signal line 21a is
External to "1" and to "0" in the system bus controller 3b.
It is assumed that they are connected. In this case, the system bus system
The control device 3a is the master and the system bus control device 3b is the thread.
Act as a slave. Data read from the memory device
The data is transmitted from the system bus together with the data valid signal line 22.
Input to the system bus controller 3 as the data signal line 13-1.
Data clock by the system clock signal 15.
Latch circuit 14 and the output of the data latch circuit 14
The signal line 16 is input to an error detection circuit 19 such as parity detection.
Is supplied to the data latch circuit 17.
You. The data signal line 13-1 has a 32-bit data section.
When the data is normal, the
In this case, the error detection circuit 19 sets the normal signal line 20 to “1”, C
The PU bus switching signal line 12 is set to "0" and an error is detected.
In this case, both signals are output with the opposite logic. If the data is normal now, the master
The normal signal line 20 in the system bus controller 3a on the side
a is “1”, and is ORed via the AND gate 24 a
The output of the gate 26a becomes "1". System clock
CPU bus selection latch 23 at the timing of signal line 15a
a is set to “1”, and is set by the AND gate 29a.
Period when the data output timing clock signal 30a is "1"
Only during the three-state buffer 31 of the CPU data bus
a becomes “1” and the data latch circuit
The contents of the output signal line 18a of the path 17a are transferred to the CPU bus.
It is output as the data signal line 8. On the other hand, when an error is detected in the data
Indicates that the normal signal line 20a becomes “0” and the gate signal 32
a becomes “0”, the system bus control device 3 a
No data is output to the PU bus. Next, the operation on the slave side will be described. If no error is detected in the data,
Normal signal line in the system bus controller 3b on the slave side.
20b is “1”, but the master mode input signal line 21
Since b is "0", the AND gate 24b becomes "0",
Moreover, the CP from the system bus controller 3a on the master side
Since the U bus switching signal line 12a is also "0", the OR gate
The output of the port 26b also becomes "0". As a result, the CPU
Gate signal 32 of data bus 3-state buffer 31b
b becomes “0”, and the system bus controller 3 b
Do not output data to the bus. Here, suppose that the master side
When an error is detected in the stem bus control device 3a, the CP
The U bus switching signal line 12a becomes "1" and the AND gate
25b and the output of the OR gate 26b become "1",
Slave instead of master system bus controller 3a
The system bus controller 3b on the side transmits data to the CPU bus.
Outputs line 8. For this reason, not only memory devices, but also
Duplication at the stem bus level becomes possible. Next, the interrupt signal line 9 and the
The generation of steps 10 and 10 will be described with reference to FIG. EXOR gate 35 and AND gate 36
Is the combination of the CPU bus switching signals 12a and 12b.
Therefore, the states of the interrupt signal lines 9 and 10 are determined. Note
If the read data from the storage device 4 is normal on both sides,
Both the signal lines 9 and 10 become inactive. Which
On the other hand, if an error is detected, the EXOR gate 35
As a result, the low-level interrupt signal line 9 becomes active,
When an error is detected on the
The level interrupt signal line 10 becomes active. The processing device 1 by these two types of interrupts
The operation will be described. [0036] Low level interrupts are subject to error detection.
The correct data was sent to the processing unit 1
Indicates the occurrence of harm. The processing device 1 is a normal program
Run the program, and break the program (usually the task switch).
Error processing). Meanwhile, high level
Is interrupted, correct data is not sent to the processing unit 1.
Processing apparatus 1 immediately performs error processing.
Use when you should. The role of the pull-up resistor 34 in FIG.
Will be explained. This resistor can be replaced by repair
Bus controller, for example, the master system bus controller.
This is significant when the device 3a is removed. At this time, error detection
Since the output signal of the output circuit 19a is not driven,
Pull-up resistor built in system bus controller 3b
34b sets the CPU bus switching signal line 12a to "1".
Fixed. This is the system bus controller 3 on the master side.
a is the same as the state where the data error is detected, and the result is
The system bus controller 3b on the slave side
Send out. The system bus control device 3 described above
The operation of the error detection circuit 6 and the CPU bus switching circuit 7
An error was detected during reading of 8 consecutive words.
This will be described with reference to FIG. In the figure, data indicated by white circles is a memory device.
The data read from 4a and the data in black circles are memos.
Indicates data read from the storage device 4b, and does not include T01.
In accordance with the timing of T14, the system clock signal line
15, the clock inside the system bus controller is
Work in a period. The figure shows the system bus controller 3 on the master side.
The third word in a, the system bus controller 3 on the slave side
b, CPU error when an error is detected in the fifth word
Switch signal line 12, gate signal 32, CPU data
2 shows the state of the data signal 8 and the low-level interrupt signal line 9. In the figure
The timing of the signal
For example, the output signal line 1 of the data latch 14 is
6 is slightly behind the rising edge of the system clock 15.
Output, indicating more realistic timing.
You. Data error detected in the first and second words
Not the gate of the system bus controller 3a on the master side
The signal 32a becomes "1" and the CPU data bus 8
03 and the system bus controller 3 at the timing of T04
a, that is, data read from the memory device 4a.
Is output. When an error is detected in the third word, T0
An error is detected at timing 4 and the CPU bus switching signal is
The line 12a becomes "1", and at the timing of T05,
Data of the system bus controller 3b on the slave side,
The read data from the memory device 4b is output,
, A low level interrupt signal 9 is output. In the fourth word, normal data is detected on both sides.
Therefore, no CPU bus switching occurs and the default
The master-side data set as default is T06
Output by The data of the fifth word has an error on the slave side.
Is detected, but the master side is normal and the CPU bus
No switching occurs, and the data on the master side remains at T0
7 is output. As shown in FIG. 4, an error is detected on the master side.
Memory device connected to the master side unless otherwise specified.
Data is output to the processing device 1 and an error is detected.
Memory device connected to the slave only when
The read data of the location is output to the processing device 1. Therefore,
Even if a changeover occurs, normal data is not transmitted to the processing unit.
It will be supplied at one timing. Also, as shown in FIG.
The gate signal line 32 of the buffer
Only the minute is in the state of "1". Set to “1” for the entire period
Then, when the CPU bus is switched, a short
It is time, but the outputs of the 3-state buffers on both sides collide
This is because As shown in Figure 5, the data is on the drive
On the data bus even after the end of
Determine the drive time required for design because it is maintained for a period
Can be FIG. 2 shows a master mode switching signal line.
As the master switching of the system bus controller 3 directly
Used, but with the addition of the master decision circuit shown in Figure 6.
Switches the master mode by the processing device 1
be able to. 6 to 6 show the operation of the master switching circuit.
7 will be described. In FIG. 7, when power is turned on, the timing
At T20, the master flip is performed by the reset signal line 42.
Flop 37 is in the state of master mode switching signal line 21
Therefore, it is set / reset, and the system bus controller 3
a, the master mode output signal line 41a is set to "1".
The master mode output signal line 41b of the bus controller 3b is
It is set to “0”. Master switching signal from processor 1
Each master flip-flop at T21 by line 38
37 is inverted synchronously, and the system bus controller 3a
The star mode output signal line 41a is set to “0” and the system bus
The master mode output signal line 41b of the control device 3b is "1".
Is set to This master mode output signal line 41 is connected to FIG.
By using as the master mode input signal line 21 of
Switching the mode of the system bus controller 3
Becomes possible. Embodiment 2 FIG. FIG. 8 relates to a second embodiment of the present invention.
In the dual memory system, CPU data is added to the first embodiment.
A bus check function has been added to further improve reliability.
It is. In FIG. 8, reference numeral 50 denotes CPU bus data 8.
Data rate for loading into the system bus controller
Circuit 51, the output signal line 1 of the data latch circuit 17.
8 and the output signal line 55 of the data receiver circuit 50 are compared.
The data comparison circuit 53 is a comparison circuit of the data comparison circuit 51.
An output signal line that outputs “1” when the results do not match, 54
Is a three-state buffer. FIG. 9 shows a system bus system for reading data.
Assuming that the operation is performed from the side of the control device 3a, the circuit of FIG.
The signal of each data comparison circuit 51 when a part fails
Line, CPU bus data 8 normality, and high level interrupt
FIG. 3 is a diagram showing a relationship between only signal lines 10. FIG. 10 shows a modification of the second embodiment of the present invention.
The output signal line 53 of each data comparison circuit 51 is
Output to the outside of the stem bus control device, and
The EXOR circuit 57 outputs a low level interrupt signal 9 and a high level interrupt signal.
And configured to generate the interrupt signal 10 of the
Similarly, FIG. 11 shows that a portion of the circuit of FIG. 10 has failed.
Sometimes the output signal line of each data comparison circuit 51 and the CPU
The normality of the bus data 8, the low-level interrupt signal 9 and the high
FIG. 3 is a diagram showing a relationship between level interrupt signal lines 10. FIG.
1, the data read is performed by the system bus controller.
3a. System bus control configured as described above
FIG. 8 shows the comparison operation of the CPU data bus of the device.
Will be explained. Data read from the dual memory device
Is temporarily latched by the data latch 17 and the comparison circuit 51
Provided to a driver circuit 31 composed of a three-state buffer
The system bus controller 3a on the master side is
1 through the driver circuit 31a.
Output to CPU bus. The data signal 8 of the CPU bus
Are the system bus controllers on both sides through the receiver circuit 50.
The data is taken into the device 3 and input to the comparison circuit 51. ratio
In the comparison circuit 51, the output of the data latch 17 and the receiver circuit
50 outputs are compared, "0" if they match, and if they do not match
The error signal line 53 is output. By the way, the master system
Master mode output signal line 41a of system bus controller 3a
Is set to “1”, the three-state buffer 5
The enable signal of 4a is inverted by the NOT circuit 52a
And "0" is given, so that the error signal line 53a is
Not output to the unit. On the other hand, the system bus system on the slave side
The master mode output signal line 41b of the control device 3b is set to "0".
Is set, the rice in the three-state buffer 54b is
The cable signal is inverted by the NOT circuit 52b to “1”.
, The error signal line 53b is
Buffer 54b, and a high level interrupt signal
The processing device 1 is notified as a line 10. Next, the middle of the data transfer path will be described with reference to FIG.
Error signal line 53 and CPU data
And the relationship between the interrupt signal line 10 and the validity of the
You. In this example, the data latch 17 and the ratio
Comparison circuit 51, driver circuit 31, and receiver circuit 50
Indicates the time of failure, and if everything is normal,
Naturally, the correct data is output on the CPU data bus.
And no interrupt is generated. Data latch 17
a or if the driver circuit 31a fails,
Data is output to the CPU data bus, which is
Error is detected by the comparison circuit and a high-level interrupt occurs
Then, the error of the read data is notified to the processing device 1. place
The processing device 1 executes the error analysis process stored in the control ROM 2.
By executing, for example, the master switching signal line 38
Output and change from the system bus controller 3a to 3b
Read the data from the memory device again.
Data latch 17a or driver circuit 31a
Can be detected. Thereafter, the system bus control device 3b becomes the master
Will work as a side. The master-side receiver circuit 50a or ratio
When the comparison circuit 51a fails, the comparison error signal line 53a
Is output internally, but the interrupt signal line 10 is output.
Does not affect operation. At this time, the CPU data bus
Since normal data is output to No. 8, there is no problem. one
On the other hand, the slave side receiver circuit 50b and the comparison circuit 51b
Or, when one of the data latches 17b fails,
Correct data is output from the master to the CPU data bus.
Despite this, the comparison error signal line 53b becomes “1”.
Thus, the high-level interrupt signal line 10 is output. At this time
The processing unit 1 also outputs a master switching signal line,
The master is switched to the stem bus control device 3b side.
To prevent unnecessary switching due to a slave side failure
The following method may be used. That is, the system
Status of the error signal line 53 in the
Stored in a register (not shown), and the processing device 1
This step is performed when the error processing stored in M2 is executed.
Check the contents of the status register. At this time, the master
If no error occurs, do not switch master
Control may be performed as follows. In FIG. 9, data reading is performed by the system.
Since it is assumed that the processing is performed from the side of the bus control device 3a,
The comparison error signal line 53b and the high-level interrupt signal line 10
Logic always matches. This is shown in FIG.
-The signal line 53b is output as the high-level interrupt signal line 10.
It is to be empowered. This is shown in FIG. 9 by #B_ERR
Indicated by the matching of the logic in the OR and HINTR columns
Have been. Next, the comparison error signal line 53 is connected to both sides of the system.
Output from the system bus controller 3
An example of generating different types of interrupts is shown in FIG.
This will be described with reference to FIG. Difference between FIG. 10 and FIG. 8 described above.
Outputs the output of the comparison circuit 51 to the outside on both sides, and
Processing unit 1 by AND gate and EXOR gate
The point is that it is generated as an interrupt signal for it. The driver circuit 31a shown in FIG.
The comparison error signal lines 53 on both sides become “1”.
The high level interrupt signal line 10 is output,
In the case of a minute failure, a low-level interrupt signal line 9 is output.
Normality judgment of data output to CPU data bus
In a sense, even when the data latch 17a fails,
Should be output, but this is
As in the first embodiment, the parity of the output of the data latch 17 is also detected.
Check circuit is added and data is switched from slave side and output.
We will try to solve it. As a result, C
As long as the data output to the PU data bus is normal
Low level interrupt signal, high level only when abnormal
An interrupt signal can be output. Embodiment 3 FIG. FIG. 12 shows a third embodiment of the present invention.
According to the present invention. In the figure, 60
Is the CPU data contained in the system bus controller 3
A bus side driver / receiver, 61 is a system bus side
The driver / receiver 62 is built in the memory device 4
The driver / receiver 63 is a
64 is built into the system bus controller 3
The parity check circuit 65 on the CPU data bus side,
The system bus side built in the system bus controller 3
The parity check circuit 66 is provided with a
Parity check circuits, 67 to 69 are parity check circuits respectively.
Status register storing the results of paths 64 to 66
, 70 is the internal bus of the system bus controller, 71 is the memo
And 72, an internal bus of the memory device 4. FIG. 13 shows a memo in the system of FIG.
FIG. 14 shows an error analysis during a write operation to the memory.
FIG. 9 is a diagram illustrating error analysis during a read operation from memory,
In the status register, ○ indicates that no error was detected, and × indicates error.
-Indicates detection. The dual memory system configured as described above
The operation of the system will be described with reference to FIG. First processing equipment
When 1 writes data to the memory device 4,
Error check codes such as parity codes
And outputs it to the CPU data bus 8. system
The bus controller 3 outputs the data with parity output from the processor 1.
The data is received by the receiver circuit 60, and the data
The parity check is performed by the parity check circuit 64, and the result is checked.
Stored in the status register 67 and received by the receiver 60
The received data passes through the internal bus 70 and is
Driver circuit 61 and output to the system bus 13.
It is. A parity check circuit 65 is provided immediately before the driver circuit.
Yes, the check result is also stored in the status register 68
Is stored. Further, the memory device 4 includes a system bus 13
From the receiver via the receiver circuit 62, and
Parity check by the parity check circuit 66
The result is stored in the status register 69, and
1 is the content of the data bus 72 in the memory device as it is
Write as data part and check code part. When writing
If an error is detected somewhere in the data path of the
1 is interrupted (interrupt signal line is not shown)
), The processing device 1 detects errors stored in the control ROM 2.
-Execute the analysis program to identify the fault location. Next, the error detection result at the time of writing is stored.
Status registers 64 to 66
An example of failure analysis will be described with reference to FIG. The failure probability is
Based on circuit size, memory is 1/10000 and bus is 100,000
1 / parity generation / check circuit and driver / reggy
Assuming that the buffer is 1 / 1,000,000, for example, memory and parity
Double failure of test circuit is 10,000 x 1 million = 1/10 billion
Assume that FIG. 13 shows a possible failure cause.
Of the combination with the highest probability of occurrence
Have been. Failure is 8 depending on the status register combination.
The type is conceivable, and case 1 is a state where no error has occurred.
It is a state. Case 2 is the internal bus of the system bus controller.
Since up to 70 is normal, the system bus 13 and driver
Path 61, a memory device receiver circuit 62, or a parity circuit.
Any failure of the inspection circuit 66 is considered,
By comparing the occurrence probabilities, it is estimated that the system bus 13 has failed.
It is. In case 3, the parity check circuit 65 is on the way.
This parity check circuit detects an injury error.
It is estimated that only 65 failures have occurred. In this case, the parity
Inspection circuits 64 and 66 are faulty and only 65 is correct
However, as in Case 2, it is determined from the probability of failure.
I do. The following case may be considered in the same manner. Subsequently, the operation at the time of reading from the memory device 4
Will be described with reference to FIG. The memory 71 has a data section
Error check code part is stored and read
The parity-added data is sent to the parity check circuit 66.
And the result is stored in the status register 69.
Stored, and then the system
13 and the system bus control device 3
This is received through the circuit 61 and the parity check circuit 6
Status check result of parity check by 5
68. Further, a driver circuit 60 for the CPU bus
Of the parity check by the immediately preceding parity check circuit 64
The result is stored in the status register 67. system
The bus controller 3 detects a parity error in the data.
Error is not detected according to the operation of the first embodiment.
The system bus controller on the side sends data to the processor 1
Is sent. An error detection result at the time of reading is stored.
Status registers 64 to 66
An analysis example will be described with reference to FIG. In FIG.
Among the possible combinations of failure points, the one with the highest probability
Is caused. Case 8 is reading from memory 71
Since an error has been detected immediately after
Possible failures or errors in the data path during writing
However, the former failure is determined by comparing the probabilities. Case
7 is correct when reading from memory,
Error has been detected, the system bus 13
In case 6, the parity check circuit 65 and the memory 71 fail.
it is conceivable that. The following case may be considered in the same manner. Embodiment 4 FIG. FIG. 15 shows a fourth embodiment of the present embodiment.
4 is a duplicated memory system according to an embodiment. 8 in the figure
0 is inside the system bus controller 3 and
An error detection circuit that detects errors in data sent to the bus
And 81, the result of the error detection circuit 80
System bus switching signal line to be transmitted to the bus controller 8
2 is a system bus switching signal line 81 from the other party and an internal
A system that operates according to the result of the error detection circuit 80
System bus switching circuit for switching the bus, 85
Is inside the memory device 4 and is read from the memory 71
An error detection circuit 84 detects an error in the data
The result of the error detection circuit 85 is transmitted to the memory device on the other side.
The memory error detection signal line 83 is a memory error
-The result of the detection signal line 84 and the internal error detection circuit 85
The system for switching the system bus
This is a system bus switching circuit. FIG. 16 shows the system bus switching in FIG.
Output data in the circuit 82 and the error detection circuit 80
This is a diagram showing the concept of switching, where reference numeral 94 denotes a system bar.
For storing the contents of the data bus 70 inside the data controller.
And a latch 90 for transmitting data to the system bus A.
3-state buffer for stem bus A, 91
3-state bus for system bus B that sends data to bus B
Reference numeral 86 denotes a three-state buffer 9 for the system bus A.
AND gate 87 for generating an output enable signal of 0
The output enable signal of the three-state buffer 91 for the system bus B is
The generating AND gate 95 is a three-state buffer 90
AND gates that generate output enable signals for both
92 is a set of system bus switching signal lines 81a and 81b
EXOR game that generates low-level interrupt by matching
Similarly, 93 is an AND that generates a high-level interrupt.
The gate. FIG. 17 shows the system bus cutoff in FIG.
Input data in the conversion circuit 83 and the error detection circuit 85.
This figure shows the concept of data switching.
Data from the memory bus A13a into the memory device 4.
The sheaver circuit 99 receives data from the system bus B13b.
Each of the receiver circuits to be loaded into the memory device 4
Data signals 76 and 77 are output. 83 is an input data signal
An error detection circuit that performs a parity check of the
Select the correct data according to the result of the error detection
And a selection circuit for outputting the signal to the internal bus 72. NOT
The input switching signal 78 which is the output signal of the port 74 is "1".
, The input data line 76 is selected, and the AND gate 75
When the input switching signal line 79, which is the output signal of
Is configured to select the input data line 77. FIG. 18 shows the processing from the processing device 1 to the memory device 4.
When data bus breaks during data write
Like bus switching by bus switching circuits 82 and 85
(A) is a normal state, (B) is a CP
A state in which the receiver in the U bus switching circuit 7a has failed;
(C) is a state in which the system bus A13a has failed, (D).
Indicates that the driver of the system bus switching circuit 82b has failed.
The data flow in the state is shown. Indicated by a broken line in the figure.
The data flow is closed by each 3-state buffer
In this state, no actual data is output. Similarly, FIG. 19 shows that the processing device 1 is a memory device.
4 when the data bus fails during reading from
PU bus switching circuit 7, system bus switching circuit 82 and
FIG. 7A is a diagram showing a state of switching buses according to FIGS.
Are all normal, (B) is a system bus switching circuit 8
2a: The receiver inside has failed, (C) is the system
The state in which the bus A13a has failed, FIG.
Data when the built-in memory 71a has failed
It shows the flow. The dual memory system configured as described above
The schematic operation of the system will be described with reference to FIG. place
When the processing device 1 writes to the memory device 4, the processing device
The write data from 1 is transferred to the CPU data bus 8
Supplied to each of the duplicated system bus controllers 3,
The system bus control unit writes data to the system bus 13.
Immediately before sending the data, the error check circuit 80
Check and send the result to the system bus switching signal.
Are exchanged with each other as line 81 and an error is detected.
When there is no system bus controller 3a on the master side,
System bus controller on the slave side
3b outputs data to the system bus B13b.
You. When an error is detected, the system bus switching described above is performed.
The signal line 81 becomes "1" and the system bus switching circuit 8
2 to the system bus 13 on the side that detected the error.
Stops output and replaces the other system bus controller
Outputs write data to the system buses on both sides. Also
In the memory device 4, the writing output to the system bus
Data is fetched from both system buses 13 and an error occurs.
A parity check is performed by the detection circuit 85, and an error occurs.
Writes unbused system bus data to memory 71
No. At the time of reading from the memory device 4,
About the data read from the duplicated memory 71,
And a parity check is performed by the internal error detection circuit 85.
Output the result as a memory error signal line 84
Mutual notification is made, and if there is no error, the memory device 4a
The memory device 4b is connected to the system bus A13a by the system bus A13a.
Data to the source B 13b, and when an error occurs,
The memory device on the generating side is sent to the system bus switching circuit 83.
Data output to the system bus is stopped
Memory device outputs read data to both system buses
I do. In addition, the system bus control device 3
Data from the error detection circuit 6
Check and check the result with the CPU bus switching signal line.
Output to each other to notify each other.
The system bus controller 3a on the data side
The read data is output to the
The system bus controller on the other side is a CPU bus switching circuit 7
Data output is stopped by the
The control device outputs on its behalf. First, the data is transferred from the processing device 1 to the memory device 4.
The detailed operation when writing data will be described with reference to FIG.
Write data from the processing device is passed through the internal bus
Data latch 94 and the error detection
A parity check is performed by the path 80. Data
The output signal of switch 94 is a three-state buffer.
Power buffers 90 and 91,
The gate signal of the buffer is connected to the master mode input signal line 21
Stem bus switching signal lines 81a and 81b and data output
It is controlled by the timing clock signal 30. D
Error detected by the error detection circuits 80a and 80b.
If not, the master side system bus control unit 3a
When the output of the D gate 86a is "1", the AND gate 87a and the
And the output of the OR gate 96a is "0".
a is "1" and the output of the OR gate 97a is
It becomes "0" and the system bus
The data is output to A13a. On the other hand, the slave system
In the bus controller 3b, AND gates 86b and 95b
Is "0" and the output of AND gate 87b is "1".
The output of the OR gate 97b is "1",
The output of the port 96b becomes "0" and the output buffer 91b
The data is output to the system bus B13b via the terminal. By the way, the system bus controller 3a
Data error is detected, the output of the error detection circuit 80a is output.
When 81a becomes "1", the output of the AND gate 86a becomes
It becomes "0" and the output of the output buffer 90a is stopped.
System bus controller 3b is the system bus from the other party
When the switching signal line 81a becomes “1”, an AND gate
The output of the output buffer 90b becomes "1".
The output is also enabled, and the system buses A13a and A13a
Output data to both sides of b. Further, in the memory device 4 shown in FIG.
Thus, the data of the system buses on both sides are
8 and 99, the error detection circuit 83
Is performing a parity check and no error is detected.
Output, the output of the error detection circuit 83-1 is "0"
The data switching signal line 78 becomes "1" and the system bus
A13a data is selectively output to the internal bus 72. on the other hand
When a failure occurs in the system bus A13a, an error detection
The output of the path 83-1 is "1", and the input data switching signal line 7
8 is "0" and the input data switching signal line 79 is "1".
As a result, the data on the system bus B13b is
Output to the switch 72. Incidentally, the error detection circuits 83-1 and 83-1
If an error is detected in both 3-2 (for example, the system
The bus 13a breaks down and the master-side receiver circuit 99
a) has failed, the input data switching signal line 78 and
79 are both "0", and the selection circuit 73a
The system bus cannot be selected. Note at this time
Incorrect data in the file 71a (this is detected as an error
Can not be written)
A situation in which data is sent to the processing device 1 may occur. This
This can be avoided by the following method. In other words, yes
If the system bus cannot be selected, the internal bus
Error data (for example, even parity
In all cases, all data is “1”, and in the case of odd parity, all
The selection circuit 73 is configured to generate “0” data).
Then, error data is forcibly written to the memory. This result
As a result, at the time of reading, the operation of the first embodiment
The system bus controller 3b processes the correct read data.
Can be sent to the processing device 1. FIG. 15 will be described again. Processing device 1 is a memo
The operation when reading data from the memory device 4 is performed by a memory device.
Internally, as in FIG. 16 in the system bus control device 3
Circuit is built in, and the data read from the memory
If there is no error in the data, the memory device 4a
The readout data is output to the memory A13a, and the memory device 4b outputs
The read data is output to the system bus B13b. one
On the other hand, reading of the memory 71b built in the memory device 4b
When an error is detected in the data, the output of the memory device 4b is output.
Buffer data output is stopped and the memory error detection signal is
No. 84b is output to the memory device 4a on the other side, and
The signal causes the memory device 4a to transfer data to the system buses on both sides.
Output data. Also, inside the system bus controller 3
There is an input data selection circuit similar to the memory device 4,
Is the internal bus for reading data from the system bus A13a.
But an error occurs on the system bus A13a side.
When detected, the read data of system bus B13b is
Output to internal bus. The memory system duplicated as described above
Data cut when some of the components fail
The state of the replacement is described with reference to FIG. 18 during the write operation.
I do. (A) In the case where everything is normal, the processing device 1
These write data are transmitted from the system bus controller 3a to the
The system bus A 13a and the system bus controller 3b
Output to the stem bus B13b, the memory device 4
Select the data of the bus A13a as the write data,
Write to the memory 71. (B) The internal circuit of the CPU bus switching circuit 7a
In the state where the sheather has failed, the system bus controller 3a
Outputs a system bus switching signal line 81a from the
The output buffer of the system bus controller 3a is closed,
The system bus controller 4b transmits data to the system buses on both sides.
And the memory device 4 is connected to the system bus A13a.
Select the data as write data and write to memory 71
Put in. (C) System bus A13a has failed
In the state, the memory device 4 stores the data of the system bus B13b.
Is selected as write data, and is written to the memory 71. (D) System bus switching circuit 82b
When the driver has failed, the system bus B13b
Although the correct data is not output, the memory device 4
There is no effect because data on the stem bus A13a is written.
No. The reading operation will be described with reference to FIG.
I do. (A) In the normal state, the memory 71
The data read from the memory device 4a
The bus A13a is connected to the system bus B1 from the memory device 4b.
3b, and the system bus controller 3a
Send the read data to the (B) Inside the system bus switching circuit 82a
The system bus controller
An error is detected by the error detection circuit 3a and the CPU bus
The switching signal line 12a is output, and the signal line
Stem bus controller 3b outputs data to CPU bus
You. (C) System bus A13a has failed
In the state, the system bus A13 is set in the system bus control device.
a is detected and the system bus B13b is read.
Using data as input data, the system bus control
The device 3a sends data to the CPU bus. (D) Memo stored in the memory device 4
In the state where the memory 71a has failed, the internal
The error detection circuit detects an error and
Outgoing signal line 84a, and the memory device 4
b sends out the read data to the system buses on both sides,
The system bus controller 3a sends data to the CPU bus.
You. Embodiment 5 FIG. FIG. 20 shows a fifth embodiment of the present invention.
According to the present invention. In the figure, 10
0 is the CPU bus mode built in the system bus controller 3.
Mode setting circuit for setting a mode, 101 is a system bus
Mode setting circuit for setting the mode of
Mode for setting the mode of the system bus
The circuit setting circuit 104 is built in the system bus controller 3.
To compare the data of redundant and duplicated system buses
The circuit 105 is built in the memory device 4 and duplicated.
This is a comparison circuit for comparing data of the system bus. FIG. 21 shows the inside of the system bus controller 3.
FIG. 1 is a diagram showing the concept of a circuit for controlling a CPU bus.
Mode setting circuit 100, data latch 17, comparison circuit
Path 51, a driver 31, and a receiver 50.
To the A bus permission signal line 106 output from the
Controls the data output of the CPU bus. FIG. 22 shows a system bus controller 3
Shows the concept of the circuit that controls the system bus inside.
The system bus A is connected to the A bus permission signal line 10.
6, the system bus B is connected to the B bus permission signal line 107.
Control the data output of the system bus. FIG. 23 shows a mode setting circuit in FIG.
FIG. 10 is a diagram showing details of 101 (same for 100 and 102).
You. In the figure, 120 is a mode setting data signal line, 1
21 is a mode setting data according to the master mode input line 21.
Selector circuit for selecting a selector signal, and 122 is a selector circuit.
The output signal line of the data circuit 121, 123
Mode latch to store, 125 stores B bus mode
The mode setting signal line 103
The contents of the output signal line 122 of the
Mode output signal lines 124 and 126 are AND gates at the subsequent stage.
And the OR gate, the final output signal
The A bus permission signal 106 and the B bus permission signal 107
Output. FIG. 24 shows the mode setting circuit in FIG.
FIG. 10 is a diagram showing an operation sequence of the embodiment.
Timing, T101 and T104 are mode setting timing
In T102, an error occurs on the system bus controller 3a side.
The detected timing, T103 is the time when the error is recovered.
Ming. FIG. 25 shows a memory device in actual operation.
4 shows the relationship between the operation and the mode of FIG.
(B) shows the details of the diagnostic operation (process 142).
The relationship with FIG. 24 is that the power-on process 140 is T1
At 00, the mode change processing 143 causes a failure to occur at T101.
145 is at T102, and mode change processing 146 is at T104.
, Respectively. The dual memory system configured as described above
The schematic operation of the system will be described with reference to FIG. Mo
Mode setting circuit 100 to 102 independently
A, B, C, and D modes can now be set.
The mode setting circuit 100 includes a system bus control device.
A system in which the device 3 outputs read data to the CPU data bus 8
The mode setting circuit 101 controls the system bus controller 3
Controls the output of write data to the system bus.
The memory setting device 102 reads the memory device 4 to the system bus.
Control to output data. System bus controller
3 controls output of data to the CPU data bus.
Mode setting circuit 100, the status of the system bus controller 3
The state of error detection by the internal error detection circuit 6,
Controlled by the CPU bus switching signal line 12 from the other party
It is. To the system bus by the system bus controller 3
Data output control depends on the state of the mode setting circuit 101 and the status.
An error detection circuit 80 inside the stem bus control device 3
Error detection status, system bus switching from partner
It is controlled by the signal line 81. In addition, the memory device 4
The output control of data to the system bus
Path 102 status, error detection inside memory device 4
Status of error detection by circuit 85, system from partner
It is controlled by a bus switching signal line 84. The output circuit of each bus includes
Compare the results, output the result to the outside, and
There is a comparison circuit for generating, and the output is
Enter the data immediately before and the output data again and compare
The system bus side has two system buses.
Compare the contents. Next, the CPU bus of the system bus controller 3
The detailed operation on the side will be described with reference to FIG. Through
In a normal operation, the mode setting circuit 100a is in the mode A,
The mode setting circuit 100b is set to mode B,
The data read from the memory device is
Latched in the data latch 17 via the internal bus 70 of the device 3
And a parity check by the error detection circuit 6.
Is performed. In the mode A system bus controller 3a
Means that an error has not been detected by the error detection circuit 6a.
For example, the output 106a of the mode setting circuit 100a becomes "1".
The read data is sent from the driver circuit 31a to the CPU data.
Output to tabus 8. If an error is detected, the mode
The output 106a of the constant circuit 100a becomes "0" and the data
Of the CPU bus switching signal line 1
"1" is output to 2a. In the mode B system bus controller 3b,
Indicates that the CPU bus switching signal line 12a from the other party is "0".
If the output 106b of the mode setting circuit 100b is
Becomes “0” and does not output data to the CPU data bus.
However, no error is detected by the error detection circuit 6b.
Sometimes, the CPU bus switching signal line 12a from the other party
When it becomes “1”, the output 106 of the mode setting circuit 100 b
b becomes “1” and the read data is transferred to the CPU data bus 8
Output to When turning on the system,
The mode setting circuit 100 is also set to mode D,
The output 106 of the constant circuit 100 is always "0",
Read data to the CPU data bus by the stem bus controller
Is not output. (It should be noted here that the CPU
Since the bus is not duplicated like the system bus,
Only one of the mode A and B system bus controllers C
Output is allowed to the PU data bus. others
Modes A and B are used for controlling the system bus described later.
The meaning is different from those. For the same reason, the CPU bus
Mode C is not used in the control. The mode A system bus controller 3a is
In addition, the own output data is transmitted via the receiver circuit 50a.
And the input signal line 55a is connected to the data latch 17a.
Mode B system comparing output signal line 18a
The bus control device 3b transmits the output data of the other party to a receiver circuit.
50b, the input signal line 55b and the data
The output signal line 18b of the latch 17b is compared. Comparison
If the result is different, the comparison error signal line 53 becomes "1".
This signal is transmitted to the mode B system bus controller 3b.
Is output to the outside via the three-state buffer 54b,
Is notified to the processing device 1 as a level interrupt signal line 10.
Then, the processing device performs the error analysis as shown in FIG. The system bus by the system bus controller 3
Since the output control to the memory is equivalent to that of the memory device,
The output control to the system bus by the device 4 is shown in FIG.
This will be described with reference to FIG. In normal operation mode, the mode
The setting circuit 102a sets the mode A to the mode setting circuit 102
b is set to mode B and read from memory
The data is transferred to the data bus via the internal bus 72 of the memory device.
Latch 94 and the error detection circuit 85
Performs a parity check. Mode A memory device
4a, no error is detected by the error detection circuit 85a.
If the output 106a of the mode setting circuit 102a is
“1” and 107a become “0”, and the read data is
Output from the inverter circuit 90a to the system bus A13a.
You. When an error is detected, the mode setting circuit 102a
The forces 106a and 107a are both "0", and the data
Signal output and the system bus switching signal line
84a is output to "1". Also when an error is detected
When there is no system bus switching signal line 84 from the other party
When b becomes “1”, the output 1 of the mode setting circuit 102a
06a and 107a are both "1" and the read data
From both driver circuits 90a and 91a.
It is output to buses A13a and 13b. On the other hand, in the memory device 4b of mode B,
If no error is detected by the error detection circuit 85b,
Output 106b of the mode setting circuit 102b is "0", 107b
Becomes "1" and the read data is
Is output to the system bus B13b. Error detected
The outputs 106b and 10 of the mode setting circuit 102b
7b are both "0" and when data output is stopped
In both cases, the system bus switching signal line 84b goes out to "1".
Is forced. If no error is detected,
These system bus switching signal lines 84a become "1".
And outputs 106b and 107 of the mode setting circuit 102b.
b are both "1" and the read data is
90b and 91b from both system buses A13a and
13b. Further, the memory devices 4 on both sides are duplicated.
The data of the system bus is transferred to the receiver circuits 108 and 10.
9 and is compared by the comparison circuit 105.
The comparison result is an error output signal of the internal error detection circuit 85.
(System bus switching signal line 84) and OR gate processing
Output to the outside, and the AND gate 93 and the EXOR gate
Conditions are taken at port 92 and the difference
And generates an interrupt signal of the specified level. Processing unit 1
Error analysis as shown in FIG.
Perform processing. Regarding the configuration and operation of the mode setting circuit,
Mode setting circuit 10 built in stem bus control device 3
The case of 1 will be described with reference to FIGS. 23 and 24.
First, when the power is turned on, a reset signal is issued at the timing of T100.
Signal 42 becomes "0" and the mode latches 123 and 12
5 is reset, the output becomes “0” and the mode setting
Roads 101a and 101b are both in mode D (initial mode).
C). In mode D, AND gate 127,
Since the outputs of 129 and 134 become “0”, the bus permission signal is output.
Signal lines 106 and 107 both output "0". Next, the processing device corresponds to T101 in FIG.
At timing, the data signals 120-1 to 120-4
And the data “1001” corresponding to the mode to be set
When the mode setting signal line 103 is output with the
The circuit 121 operates according to the state of the master mode input line 21.
Two of the input data 120 are selected. Here cis
The master mode input line 21a of the system bus controller 3a is
Since it is “1”, the output signal 122-1 of the selector circuit is output.
a, input data 120-1 is the output signal of the selector circuit.
No. 122-2a receives input data 120-3,
On the other hand, the master mode input line 2 of the system bus controller 3b
Since 1b is “0”, the output signal 12b of the selector circuit is
The input data 120-2 is input to the selector circuit 2-1b.
Input data 120-4 is output to the output signal 122-2b.
The mode setting circuit 101a sets the mode to the mode A.
The constant circuit 101b is set to mode B. Conversely,
Mode A means that the mode output signal 124a is "1"
The output signal 126a becomes "0" and the bus permission signal line 10
The mode in which "1" is output to 6a and "0" is output to 107a
Can be defined. Similarly, in mode B, the mode output signal 124
b becomes “0”, the mode output signal 126b becomes “1”,
"0" is applied to the bus permission signal line 106b, and
“1” is output. By the way, from T102 to T103 in FIG.
Timing, that is, the mode of the system bus controller 3a
A is a state in which the system bus controller 3b is in the mode B
The error detection circuit 80 on the system bus control device 3a side
a detects an error, the internal error signal line 81a
It becomes "1" and the AND gates 127a, 129a, 13
4a is "0", A bus enable signal line 106a and B bus enable
The signal lines 107a are both "0". Hand system
In the bus controller 3b, the system bus switching signal line 81a
(Logically the same as the internal error signal 81a) becomes "1"
Therefore, the output of the AND gate 134b becomes “1”.
A gate, which is the output of the OR gates 132b and 133b
Bus enable signal line 106a and B bus enable signal line 107a
Both become "1". Further, the processing device is T104 in FIG.
, The data signals 120-1 to 120-
Data "0101" corresponding to the mode to be set to 4
When the mode setting signal line 103 is output with the
Mode latches 123a and 125 in bus controller 3a
a are both "0" and the mode setting circuit 101a
Returning to the mode D, the bus permission signal lines 106a and 107a
It becomes "0" on both sides. On the other hand, in the system bus control device 3b
Mode latches 123b and 125b are both "1".
And the mode setting circuit 101a is set to the mode C,
The bus permission signal lines 106b and 107b are both "1".
Become. In the above described dual memory system,
Using the mode setting circuit allows diagnosis, replacement, recovery, etc.
Processing can be performed easily. In the memory device 4
An example using this function will be described with reference to FIG.
You. The duplicated memory devices are respectively A system and B system.
The mode settings are changed in synchronization with each other.
While processing. First, note 140 on both sides in process 140
When the power is turned on to the
Both sides are set to mode D, and both memories are
Data is not output. Next, writing and reading in process 142
FIG. 25 illustrates the initial diagnosis of the memory by the comparison check.
I will tell. To diagnose memory, duplicated notes
Write data must be read independently of the storage device
Therefore, first, in the process 142-1a, the memory device of the A system is
In mode C, the memory device of system B is
Mode D, and the read data is
And output the data to the memory device in process 142-2a.
Write, read, and compare data. For this reason,
The memory device of the A system is diagnosed. At this time,
Data is also written to the memory device of system B,
It has no effect on the diagnostic results of the Tohoku group. Next, in process 142-3, A
Set the system memory device to mode D, and set the system B memory device
The mode is set to mode C, and the memo of system B is set in process 142-4b.
The device can be tested. The initial diagnosis of the memory device by the process 142
Upon completion, the memory device of the A system is set to the mode in the process 143.
To set the memory device of system B to mode B
More normal operation processing 144 is performed, that is, the system bus
A-system memory device sends read data to A13a
A memory device of the B system is read on the system bus B13b.
Send out data, and if an error is detected in either
Duplex, with opposite side sending data to both system buses
Memory operation. Failure of the A system due to failure 145a
If the memory device fails, the B-system memory device
While responding with the data, the processing unit 1
The analysis is performed, and if it is determined that repair and replacement are necessary, the process 146 is performed.
To set the memory device of system A to mode D and the memory device of system B
By setting the device to mode C, the memory
Device is disconnected from the system bus. After this
Also, the memory device of system B reads out data to the system buses on both sides.
147a of the A system
Can be implemented. Replacement of new memory device with system A
A, the memory device of the A system will be
Mode D, and the normal B
Read data from the memory device of the system
A copy operation for writing to the memory device is performed. Copy complete
When the processing is completed, the memory device of the A system is set to the mode A
Next, the memory device of system B is set to mode B,
The operation can be restored to the redundant memory operation. Embodiment 6 FIG. FIG. 26 shows a sixth embodiment of the present invention.
According to the present invention. In the figure, 170
Are built in the memory device 4 and write and read the memory.
A permission flag for controlling the overflow, 171 is a memory
A control circuit for generating access timing, 172 is a memo
Address determination to determine the access address to the
Another circuit, 173, forcibly writes error to memory 71
177 is a duplicated system.
It is an input / output control device connected to both of the buses. FIG. 27 shows the internal structure of the memory device 4.
In the figure, the permission flag 170, the address discrimination circuit 172,
Driver 220, receiver 221, parity generation circuit 23
9 and a memory 71. In the figure,
Read permission flag 170-1, write permission flag 1
70-2, a parity generation permission flag 170-3
And write / read to / from memory with a combination of these outputs.
Control the generation of parity. FIG. 28 shows details of the address discriminating circuit shown in FIG.
The common space designation register 231, individual empty
Interval designation register 232, I / O address determination circuit 23
0, comparison circuits 233 and 234, AND gate 237
And a common space write signal line 21 as an output signal.
0, individual space write signal line 211, common space read signal
A line 212 and an individual space read signal line 213 are generated. FIG. 29 shows the state when accessing the system bus.
FIG. 4 is a diagram showing divisions of an address space, where 200 is the entire memory space;
201 shows the entire I / O space, and FIG.
(B) shows the assignment at the time of single operation.
I have. The memory space further includes a common access space 202
It is divided into individual access spaces 203. FIG. 30 shows that the memory device in FIG.
FIG. 6 is a diagram showing a state transition performed by a lag 170.
In accordance with the combination of the permission flags, the disconnection operation state 18
1, normal operation state 183, restoration operation state 184, and protection
Defined in the operation state 185, error occurrence or permission
Transition between the states is performed by rewriting the flag. Detachment
Operation state 181 cannot be written or read, normal operation
State 183 indicates that both writing and reading are possible, and a repair operation state
184 is for writing only, and the protection operation state 185 is for reading
It is in a state where only the work is possible. FIG. 31 shows the error injection circuit 173 and the individual space.
Diagnostic area of memories 71a and 71b by access
Inject different data and error conditions into
Indicates data read by spatial access
It is. FIG. 32 shows an example in which the address is stored in the memory device 4.
An error detection circuit 176 is provided, and its output is
And if an error is detected on the other side, an error
Concept of configuration to store correct address in address register
FIG. 33 shows details. The dual memory system configured as described above
The schematic operation of the system will be described with reference to FIG. The permission flag 170 in the memory device 4
Read enable flag, write enable flag and parity generation
The address discriminating circuit 1 is composed of three bits of a permission flag.
72 determines the common access space and the individual access space.
U. Writing using the common access space from the processing device 1
When performing the operation, if the write enable flag is "1",
Parity generation regardless of the state of the parity generation enable flag
To write to the memory 71, and
If the lag is "0", no writing is performed. Also processing equipment
Performs a write operation using the individual access space from device 1.
At this time, regardless of the state of the write enable flag, the memory device 7
1 is written, but the parity generation permission flag is
If "0", the memory device 7 does not perform parity generation.
1 is written. Next, the processing device 1 uses the common access space.
When reading is performed, the read permission flag is set to “1”.
If there is, read it out, and if the read permission flag is "0"
If there is, no reading is performed. Also, individually from the processing device 1
When performing read using access space, read
Reading is performed irrespective of the state of the permission flag. The input / output control unit 177 has both system buses.
And the system bus switching circuit is implemented.
It has the same configuration as the system bus control device in Example 5,
When fetching the read data from the memory device 4,
Use the system bus data on the side where no error has occurred.
Use. Next, the permission flag 170 and the address discrimination circuit
172, the circuit configuration and operation of the error injection circuit 173
This will be described with reference to FIGS. 27 and 28. Permission flag 1
70 is a read permission flag 170-1, a write permission flag
170-2, composed of a parity generation permission flag 170-3
And the permission flag output from the address determination circuit 172.
Input from the system bus in accordance with the
The contents of the data signal lines 224-1 to 224-3 are latched.
Touch. In the initial state, all signals are reset by the reset signal 42.
The lag is initialized to "0". Read data to system
The gate signal 222 to be output to the bus is read enabled.
A read enable signal line 214, which is a flag output, and an address
Common space read signal 21 which is the output of the
2 and the individual space read signal 213. Ma
Read in the individual space, the individual space read signal
Since 213 becomes “1”, the function of the OR gate 219
The read permission signal line 214,
The gate signal 222 of the bus circuit 220 becomes “1”,
The read data from the memory 71 is output to the system bus.
On the other hand, when reading from the common space,
Even if the output signal 212 becomes “1”, the AND gate 21
8 if the read enable signal line 214 is not "1".
Read data is not output to the system bus. In writing to an individual space,
Indicates that since the individual space write signal 211 becomes "1",
By the function of the R gate 217, the write enable signal line 215
Memory write signal line 162 becomes "1" regardless of the state of
Thus, data is written to the memory 71. Meanwhile, common
When writing to space, the common space write signal
Even if the line 210 goes to “1”, the existence of the AND gate 216 remains.
The write enable signal line 215 is not "1".
The memory write signal line 162 does not become “1” and the memory 71
Is not written to. By the way, parity generation times
The path 239 is controlled by the parity generation permission signal line 163.
Has a function to control parity generation.
When the enable signal line 163 is "1", the parity data is normal.
Is generated, and when "0" is generated, an error occurs.
Shall be So writing in the common space
Is always “1” since the common space write signal line 210 becomes “1”.
Parity is generated correctly, but individual access is empty.
In the meantime, the parity enable flag signal line 338 is set to “1”.
The correct parity is generated only if
You. If this function is used in the write operation of the individual space,
Intentionally write data that causes a parity error in memory 71
Operation, that is, error injection can be performed. Further, the above-mentioned address determination circuit 172 is
28, and an I / O address determination circuit 230
Is set for register access to the memory device.
And decode the unique address. Here the system
Bus address signal line 13-2, master mode input line
21, the condition of the write signal line 13-4 of the system bus
The common space designation register setting signal line 235, the individual space
The designated register setting signal line 236 and the permission flag setting signal
The signal 225 is output. The common space register uses the setting signal
The value of the data signal line of the system bus is latched by the line 235.
The individual space register 232 includes a setting signal line 236.
Latch the value of the data signal line of the system bus
You. When the memory space is accessed from the processing device 1,
Address signal line 13-2 on the system bus and the common space finger
The content set in the constant register is compared by the comparison circuit 233.
If they match, the common information access signal 228 becomes “1”.
At this time, if the write signal line 13-4 is "1",
Common space write signal line by AND gate 237-3
210 is “1” and the read signal line 13-3 is “1”.
In this case, the common space read signal is output by AND gate 237-4.
The line 212 becomes “1”. Similarly, individual space designation cash register
The setting contents of the star are compared by the comparing circuit 234, and when they match,
When the individual signal access signal 229 becomes "1", the individual space
Write signal 211 or individual space read signal line 213
Becomes “1”. Address discriminating circuit 1 operating as described above
72, the address space of the memory device 4 is
An example of assignment will be described with reference to FIG. (FIG. 29
Here, entities represented by 200 to 207 each have a width.
It is a memory area with. ) Fig. 29 (A) shows the duplex
In the setting example when operating as a memory,
The common access register is stored in the common space register 231a.
Set address 202-1 of memory A / B space, and
Address of the individual access memory A space is added to the inter-register 232a.
Address 203-1 is set. Next, for the memory device 4b
The common access memory A in the common space register 231b.
/ B space address 202-1 is set, and the individual space register is set.
Address 232b of the individual access memory B space
03-2 is set. With this setting, the common space 202-
In the access to the memory 1, the memory device 4a and the memo
And the individual access space 20
In accessing 3-1, the memory device 4a
In the access to the individual space 203-2,
Only the memory device 4b is targeted, and
Operation becomes possible. Also, as shown in FIG.
The common space register 231a is set to the common empty for the device 4a.
At the address 202-3 in the inter-access memory A space,
The common space register 231b is common to the storage device 4b.
Set to address 202-4 of space access memory B space
Then, access to the common address space 202-3 is performed.
Then, the memory device 4a is stored in the common address space 202-4.
Access to the memory device 4b is enabled,
Double the memory capacity compared to dual memory operation
Can be provided. Next, the permission flag 170 described above is
From the power-on using the
Normal operation, as well as repair and repair / replacement of faulty memory
Is defined by the combination of the read enable flag and the write enable flag.
FIG. 30 will be described together with the defined state transition. First
The normal operation state 183 is a read permission flag as a state definition.
And the write permission flag is “1”, and the restoration operation state 184 is
The read permission flag is "0" and the write permission flag is
“1”, the protection operation state 185 indicates that the read permission flag is
When "1", the write enable flag is "0", and the disconnection operation state
181 indicates that the read permission flag and the write permission flag
Set the status to “0” and turn off the system power.
Or the memory device has been removed from the system 18
0 is supplementarily defined. First, when the system is turned on, the state
Transition from 180 to transition 181 due to transition 186
I do. In this state, each memory device has its own
Write and read to / from memory 71 using
Memory diagnosis 188 such as read-out and comparison check,
If it is normal, correct by the transition 189 of the diagnosis completion at power-on.
It shifts to the normal operation state 183. In state 183, the memory
The device performs a duplex operation, when no error occurs, and
When a data parity error occurs, the state 183 is set.
Stay. Data parity errors occur repeatedly
And the memory device by the transition 191 for the fault diagnosis.
Move to the disconnection state 181, but if an error
The other memory device remains in the normal operation state 183. Normal memory device is in state 183, failed
If the memory device is in the detached state 181,
For the memory device, whether or not it can be repaired is determined by diagnostic processing 188.
On the other hand, during the diagnostic operation by the processor 1,
Access to the memory device by the control device 177 is a common space
The normal memory device responds
Normal operation is guaranteed. Diagnosis determined to be unrepairable
If it is, the maintenance personnel will replace it with a new memory device.
New memory devices are first detached by insertion
The state transits to the working state 181 and is diagnosed. By the way
When the state shifts to the disconnection state 181, the normal memory device
Differences in the contents of
Cannot move to state 183. So at the end of the diagnosis
Transition 196 to the restoration operation state 184.
In the repair operation state 184, the memory space is changed from the normal memory device to the common space.
Read data by writing and write by common space access
To both the normal memory device and the memory device to be repaired.
Write data. Copy processing 194 of all areas is completed
And the transition to completion of the restoration 193,
The device enters the normal operation state 183 and returns to dual memory operation.
To old. During this time, the memory device by the input / output control device 177
Since access to the storage is performed in a common space,
The write operation is performed on both memory devices and the read operation
Operation is normal with normal memory device in state 183 responding
Operation is guaranteed. In the normal operation state 183, the address parity is
When a memory error occurs, the memory device
During the data, the memory contents of the address
Immediately set the read permission flag to “0” and start reading.
The operation is prohibited, and the state is shifted to the restoration operation state 184. Address
Recovery operation state 184 after a security error has occurred.
The write to the failed memory device continues.
Therefore, until the restoration processing by the processing apparatus 1 starts, the
The difference between the contents of a new memory device and that of
Only the place where After performing the necessary restoration processing there,
The normal operation state 183 can be returned. The usage of the protection operation state 185 will be described.
I will tell. Mode switching from the processing device 1 to the protection operation state
The process proceeds to the replacement process 197. For example, system bus 1
Diagnosis of failure of input / output control unit 177 connected to 3
This device will write correctly to the memory device.
Does not always execute, involves writing to the memory device
If the diagnosis is executed carelessly, the contents of the memory 71 will be destroyed
Can. Therefore, one of the duplicated memory devices is preserved.
Protection operation state 185 to prevent destruction of memory contents
Post-diagnosis is executed, and after the diagnosis is completed, the
The contents are copied from the memory device to the memory device in the normal operation state 183.
I will be. As a result, even if the I / O controller
Can be restored to normal memory even if illegal write operation is performed
Noh. If the I / O controller operates normally,
Normal operation with the write enable flag remaining "1".
Since the data is written to the memory device in the operation state 183,
The operation of the I / O controller can be diagnosed by checking the contents.
You. Next, the error injection circuit shown in FIG.
Error injection status used and diagnosis method using this function
The method will be described with reference to FIGS. Figure
The area 71-1 in 31 is a normal area for programs and data.
Data is stored, and the areas 71-2 to 71-5 are stored in the diagnostic area.
Used as an area. First, the parity permission of the memory device 4a is
The enable flag is set to “1” and the individual space of the memory device 4a is set.
Data “8888” is stored in area 71-2a by access
Write data “AAAAA” to the area 71-4a.
Thus, normal data is generated. Next, the memory device
4a is set to "0" and the memory device
The data is stored in the area 71-3a by the individual space access of the device 4a.
Data “B999” in the area 71-5a.
By writing B ”, the data including the parity error
Data is generated. Similarly for the memory device 4b
Indicates that the data “CCC” is stored in the areas 71-2b and 71-3b.
C "and the normal data of" DDDD "are stored in the area 71-4b.
And 71-5b contain data "EEEE" and "FFF".
Write the data including the parity error of F ". As described above, the normal data and the parity
With the data containing the
And the like, the processing apparatus 1 makes the diagnosis area
If an error occurs in the memory by reading,
Output the contents of the normal memory,
A high-level interrupt occurs if an error is detected
The function (operation in the fourth embodiment) can be diagnosed. Ie
If the function is normal, the memory in reading the area 71-2
71a responds and data "8888" is stored in the area 71-3.
In reading, the memory 71a has an error, so the memory 71b
Normal data “DDDD” is read from the area 71-5.
Now, both memories have errors, so a high level interrupt
appear. Error detecting means 85 in the memory device 4a
If a does not operate normally, read the area 71-3
Then, the error data “9999” is read out,
The location can be determined. Next, FIG.
A brief description will be given using 32. From the processing device 1 to the memory device
When address 4 is accessed, the address signal of the memory
Is performed by the address error detection circuit 176.
This result is sent to the other memory device for address error detection.
Output as output signal line 175 and detect error
The read side sets the internal read permission flag to “0” and reads
Prohibit putting out. On the other hand, the other party's address error signal line 17
5, the memory device that detects the change in address 5
-Stored in the address register 174,
The processing device 1 that knows the occurrence of the address error
Execute the failure analysis recovery program stored in OM2
The memory address at which the error occurred to the normal side memory.
Read from error address register 174 in memory device
You. Reads the contents of the memory indicated by this address and
By writing, the contents of the memory where the error occurred
Restore normal data. Of the above operations, address error detection and
For details of the error address register, refer to FIG.
Will be explained. The address error detection circuit 176a
Parity check of the address signal line 13-2a on the
Address, and if an error is detected, an address error will occur.
The signal line 175a outputs "1". This signal is internally
Resets read permission flag 170-1a to "0"
At the same time, the write signal line 1 is
62 is set to "0" to prohibit writing to the wrong address.
Stop. On the other hand, the address error occurs in the memory device 4b on the other side.
Is detected, an address error signal from the other party is sent.
Signal line 175b becomes "1" and the address signal line at this time
13-2a is stored in the error address register 174a.
It is memorized. Also, an address error occurred during reading
In this case, the memory error detection signal line 84 in FIG.
If the corresponding signal is output,
The reading device outputs the read data.
Outgoing data can be guaranteed. Moreover, an address error occurs
In the memory device that was written, only the part where the error occurred was rewritten.
It is simply not repaired and can be easily repaired. Address
When an error occurs, an EXOR gate
92 and an AND gate 93 for detecting an address error
It is generated under the conditions of signal lines 175a and 175b. either
E if an address error occurs in one of the memory devices
The output of the XOR gate 92 becomes “1” and the low level
A write signal 9 is output, and the address is stored in both memory devices.
If an error occurs, the output of AND gate 93 is
It becomes “1” and a high level interrupt signal 10 is output.
You. A low-level interrupt indicates an errored access
Address error register in memory device with normal address
Indicates that the data is stored in the
Level interrupts have an error access address.
Indicates that the restoration process is impossible because it cannot be specified. Embodiment 7 FIG. FIG. 34 shows a seventh embodiment of the present invention.
In the memory device of the redundant memory system according to
FIG. 9 is a diagram illustrating error detection. In the figure, 240 is
Receiver 241 for inputting dress is generated in advance
Error upper limit value to set the upper limit
The register 244 writes a value to the error upper limit register 241.
Error upper limit register setting signal line 245
The error detection circuit 247 is an output of the error detection circuit 245
Is incremented by the error detection signal 246 which is
And decremented by an external error correction signal line 256.
Error cumulative counter to be incremented, 249 is the upper error limit
Output of the value register 241 and the error accumulation counter 247
Compares and outputs two types of interrupt signal lines according to the comparison result
The comparison circuit 252 performs the address in which the error occurs.
Error address registers for storing
57 generates a write signal 258 of the error address register.
The write control circuit 254 that is
Select and output the data stored in the dress register 252.
The selector 259 outputs the output signal 2 of the selector 254.
When the signal for selecting 55 is "0", the memory read
When the read data 233 is “1”, the error address
When the register 252-1 is "2", the error address register
Control for selectively outputting the contents of the master 252-2.
This is a selector switching signal. Error upper limit value register
Data setting signal line 244, error correction signal line 256, select
The data switching signal 259 is, for example, a
33, the address judging circuit 172 accesses the processing device.
The address is generated by decoding the address. Error detection operation configured as described above
Will be described with reference to FIG. First, when power is turned on
Is that the error accumulation counter 247 is initialized to “0”,
Next, the upper limit of the error built into the memory device from the processing unit
Error register upper limit register setting signal line
The same value as the number of error address registers by 244
(“2” in the embodiment). After this normal memory
When the access operation is performed, the selector switching signal 259 becomes
“0” is output, and the read data from the memory 71 is read.
The data 223 is parity-checked by the error detection circuit 245.
Check is performed and if no error has occurred, the selector 2
54 and the driver circuit 220 via the system bus 1
Output to 3-1. Error detection when an error is detected
The signal line 246 becomes “1” and the error accumulation counter 24
7 is incremented. In the comparison circuit 249,
The value set in the error upper limit value register 241 described above
And the contents of the error accumulation counter 247 are compared.
The value of the error accumulation counter is
If the value is not exceeded, the low-level interrupt signal line 9
If it exceeds “1”, the high-level interrupt signal line 10
Set to “1”. The write control circuit 257 has an error
When the detection signal line 246 becomes “1”, error accumulation
According to the content of the counter output signal 248, the address signal
Which error address register to write the contents of 251
Is performed. In other words, error accumulation in the initial state
Since the content of the product counter 247 is "0", the write signal
When the line 258-1 is output, the error address
Error address is written to register 252-1 and twice
The contents of the error accumulation counter 247 when an error occurs
Is "1", so the write signal line 258-2 is output.
The error address register 252-
2 is written with an error address. In this way,
The address where the error occurred is stored in the error address register 252.
And the processing unit sends a low-level interrupt
Error address register
When the access of 252-1 is performed, the selector switching signal
259 becomes "1" and the error address register 252-
1 passes through the selector 254 and the data driver 220.
Output to the system bus. Processing equipment is like this
To find the address where the error occurred.
Read the data from the memory indicated by the address
Parity error occurred by writing to address
Repair the contents of memory. This post-processing device corrects errors
The content of the error accumulation counter 247 is changed over the signal line 256.
Decrement. By the way, the processing unit has a low level interrupt
Access to the memory device until the
And a parity error occurs at a different address.
Error is less than the number of error address registers.
Then, the generated address can be stored. error
When an error occurs beyond the number of address registers
Is a high-level interrupt signal line of the comparison circuit 249 described above.
Is "1" and an unrecoverable serious fault occurs in the processing unit.
And a device such as the mode setting circuit described in the fifth embodiment.
Using the function, the corresponding memory device is separated. Embodiment 8 FIG. FIG. 35 shows an eighth embodiment of the present invention.
The dual memory system according to
Normal input having only a single bus via the adapter 261
FIG. 3 is a diagram showing a state where an output control device 260 is connected. Figure
36 and FIG. 37 show details of the duplex bus conversion adapter 261.
The configuration is shown. In FIG. 36, reference numeral 263 denotes an address signal.
The driver / receiver circuit 264 is a driver for data signals.
269 is an ordinary input / output control device.
0 is the address pattern when accessing the system bus.
271 is a parity generation circuit for generating parity.
A parity generation circuit 270 for generating data parity
Access normal I / O controller from system bus
Sometimes, check the parity of the duplicated address bus,
Parity check selection to select the correct address
Circuit, similarly 272 is a parity for selecting data
This is an inspection selection circuit. In FIG. 37, reference numeral 276 denotes a normal entry / exit.
An address area that can be accessed by the force control device 260 is set.
The address area register 278 for setting
The output control device 260 tries to output to the system bus
Address and the contents of the address area register 276
Comparison, and the result indicates that the system bus driver
This is a comparison circuit for controlling the operation. A dual memory system configured as described above
The outline of the operation related to the input / output control device of the system is shown in FIG.
Will be described. The input / output control unit 177 has a dual memory system.
The system is designed for
Access to the service. On the other hand, normal
The input / output controller 260 is aware of the redundant memory system.
Not an existing one, itself a single system bus
To the redundant bus conversion adapter
In addition to duplexing with the
Code code, address check, etc.
Has been improved. Next, details of the duplex bus conversion adapter 261 will be described.
The detailed operation will be described with reference to FIG. Normal I / O control
The device 260 is an address that does not have a parity code.
The signal line 262-2 and the data signal line 262-1 provide
Connected to the multiplexed bus conversion adapter 261
Control device accesses memory device 1 via system bus
To generate a parity on the address signal line 262-2.
The parity signal is added by the circuit 269 and the address signal is
Line 265, both sides via the driver circuit 263-1
Address signal lines 13-2a and 13-2
Output as b. The data signal line 262-1 has
A parity code is added by a parity generation circuit 271,
It becomes the data signal line 267, and the driver circuit 364-1
Address signal lines 13-1a to the system buses on both sides through
And 13-1b. On the other hand, input and output from the duplicated system bus
If the force control is accessed, the system bus
Dress signal lines 13-2a and 13-2b are receiver circuits
263-2, and input to the parity check selection circuit 270.
No error occurred as a result of parity check
Side address signal 266 is selected and normal input / output control
Output as address signal line 262-2 for device 260.
Is forced. Similarly, the data signal line 13-1 of the system bus
a and 13-1b are input to the receiver circuit 264-2.
Parity check selection circuit 272
As a result, the data signal 26 on the side where no error has occurred
8 is selected and the data for the normal input / output
Output as the data signal line 262-2. The parity check selection circuit 270 uses the add
An error is detected on the address signal line, and the correct address is selected.
If not, the address error signal line 274
Data signal on both sides by parity check selection circuit 272
If an error is detected in the line and the correct data cannot be selected
In this case, the data error signal lines 275 are output
A low level interrupt signal is output by the R gate 273
You. At this time, writing to the normal input / output control device 260 is performed.
Since the read signal line (not shown) is output,
The force control device does not start operation, and the software of the processing device 1 is not activated.
A retry process is performed. Next, with reference to FIG.
An operation for restricting access to 60 will be described. Address
The access area register 276 is accessed by the input / output control unit 260.
To specify the range of memory addresses that can be used
In this case, the processing device 1 performs input / output with respect to the input / output control device 260.
Prior to the start of the operation, the address area register setting signal 2
82, the contents of the data signal line 262-1 are addressed.
Set in the area register 276. Input / output controller 260
Is activated and transfer to memory occurs,
Device 260 accesses address signal line 262-2.
Output memory address. At this time, the comparison circuit 278
Within the range set in the address area register 276 described above.
It is determined whether or not the driver output is available.
Set the enable signal line 279 to “1” to access the system bus.
Driver output enable signal line 2
79 is set to "0" to prohibit access to the system bus
You. The OR gate 281 detects addresses outside the range.
Access, the low-level interrupt signal line 9
Set to "1" to notify the processing device. In the above embodiment, the data of the memory device
Explained by parity data as check code
However, this is not parity data but ECC code
Can be realized similarly. As described in detail above, according to the present invention,
Transfer error detection means can detect errors in the data being transferred.
Detected, and the error status register stores the detection result.
This makes it possible to diagnose error locations. Also, C
PU bus switching circuit holds error status register
Decide whether to output data to CPU bus according to the contents
Switching can be performed without overhead.
You. At this time, the parity check is performed in the middle of the data transfer path.
The parity generation circuit needs to be implemented in the processing unit.
Required, and the circuit configuration of the entire system is simplified.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an overall configuration of a dual memory system according to a first embodiment of the present invention. FIG. 2 is a diagram showing a configuration of an error detection circuit 6 and a CPU bus switching circuit 7 in FIG. FIG. 3 is a diagram showing a correlation between an error occurrence state and a CPU bus switching signal line 12 and interrupt signal lines 9 and 10 in FIG. 1; FIG. 4 is a timing chart showing an operation of the circuit of FIG. 2; 5 is a diagram showing timings of a data signal 18 and a gate signal 32 in the circuit of FIG. FIG. 6 is a diagram showing details of a master determination circuit 5 in FIG. 1; FIG. 7 is a timing chart showing an operation of the master determination circuit 5 of FIG. FIG. 8 is a diagram illustrating a system bus control circuit of a redundant memory system according to a second embodiment of the present invention. FIG. 9 is a diagram showing an operation when a part of the circuit in FIG. 8 fails. FIG. 10 is a modified example of the system bus control circuit according to the second embodiment of the present invention. 11 is a diagram showing an operation when a part of the circuit in FIG. 10 has failed. FIG. 12 is a diagram showing an arrangement of an error detection circuit and a status register in a redundant memory system according to a third embodiment of the present invention. FIG. 13 is a diagram showing a method of determining a failure portion at the time of writing data to the memory in the redundant memory system in FIG. 12; FIG. 14 is a diagram showing a method of determining a failure point at the time of memory reading of the redundant memory system in FIG. 12; FIG. 15 is a block diagram showing an overall configuration of a redundant memory system according to a fourth embodiment of the present invention. 16 shows a system bus 13 of a system bus switching circuit 82 incorporated in the system bus control device 3 in FIG.
FIG. 4 is a diagram illustrating a portion for switching output to a power supply. 17 is a diagram showing an input switching portion from the system bus 13 of a system bus switching circuit 83 built in the memory device 4 in FIG. 15; 18 is a diagram showing switching of a data bus when a processing device in the duplicated memory system in FIG. 15 performs writing to the memory device. 19 is a diagram illustrating switching of a data bus when a processing device in the dual memory system in FIG. 15 performs reading from the memory device. FIG. 20 is a block diagram showing an overall configuration of a duplicated memory system according to a fifth embodiment of the present invention. 21 is a diagram showing a CP of the system bus control device 3 in FIG. 20;
It is a block diagram around a U bus. FIG. 22 is a configuration diagram around a system bus of the system bus control device 3 in FIG. 20; 23 is a detailed diagram of a mode setting circuit 100 built in the system bus control device 3 in FIG. FIG. 24 is a timing chart showing an operation of the circuit of FIG. 23; FIG. 25 is a diagram showing a mode transition in the memory device in FIG. 20; FIG. 26 is a block diagram showing an overall configuration of a duplicated memory system according to a sixth embodiment of the present invention. FIG. 27 is a diagram showing an internal configuration of a memory device 4 in FIG. 26; FIG. 28 is a diagram showing details of an address determination circuit 172 in FIG. 26; FIG. 29 is a diagram showing allocation of an address space of the memory device 4; FIG. 30 is a diagram showing a state transition of the memory device 4 according to a combination of permission flags. FIG. 31 is a diagram showing an error injection state in the memory by the error injection circuit 173 in FIG. 26; FIG. 32 is a block diagram showing an overall configuration of a redundant memory system in which an address error detection function is added to the sixth embodiment of the present invention. FIG. 33 is a diagram showing an internal configuration of a memory device 4 in FIG. 32; FIG. 34 is a diagram illustrating a data error detection method according to a seventh embodiment of the present invention. FIG. 35 is a block diagram showing an overall configuration of a redundant memory system including a redundant bus conversion adapter 261 according to an eighth embodiment of the present invention. FIG. 36 shows a duplex bus conversion adapter 261 shown in FIG. 35;
FIG. 3 is a diagram showing an internal structure of the device. FIG. 37 shows an address area register 27 in FIG.
6 is a diagram showing a duplex bus conversion adapter 261 to which 6 is added. FIG. [Description of Signs] 1 processing device (CPU), 2 control ROM, 3 system bus control device, 4 memory device, 5 master determination circuit,
6 Error detection circuit, 7 CPU bus switching circuit, 8
CPU data bus, 9 low level interrupt, 10 high level interrupt, 11 CPU address bus, 12 CP
U bus switching signal line, 13 system bus, 19 error detection circuit, 20 normal signal line, 21 master mode input signal line, 30 data output timing clock signal,
31 3-state buffer, 34 pull-up resistor, 3
5 EXOR gate, 36 AND gate, 38 master switching signal line, 41 master mode output signal line, 4
2 reset signal line, 51 data comparison circuit, 53 comparison error signal line, 60 to 62 driver / receiver, 6
3 Parity generation circuit, 64-66 Parity check circuit, 67-69 Status register, 70 System bus control device internal bus, 71 memory, 72 memory device internal bus, 73 selection circuit, 78 Input data switching signal line, 80, 85 Error Detection circuit, 81 system bus switching signal line, 82, 83 system bus switching circuit, 84 memory error detection signal line, 100 to 102
Mode setting circuit, 103 mode setting signal line, 104,
105 comparison circuit, 106 A bus permission signal line, 107
B bus permission signal line, 113 comparison error signal line, 12
0 mode setting data signal line, 121 selector circuit,
123, 125 mode latch, 140 power-on processing, 141, 146, 148 mode D state, 142
Diagnostic processing, 143, 151 Mode A state, 144, 1
52 normal operation, 145 failure occurrence, 147 repair exchange processing, 149 diagnosis processing, 150 memory copy processing,
153, 161 mode B state, 156 mode C state, 157 normal operation, 162 memory write signal,
163 parity generation permission signal line, 170 parity permission flag, 172 address discrimination circuit, 173 error injection circuit, 174 error address register, 175
Error address signal line, 176 address error detection circuit, 177 input / output control device, 180 power-off state,
181 disconnection operation state, 183 normal operation state, 18
4 Recovery operation state, 185 protection operation state, 186 card insertion / power-on operation, 187 card removal / power-off operation, 188 memory diagnosis operation, 189 power-on diagnosis completed, 190 no error / single data error operation,
191 Duplicate data error occurrence, 192 address error occurrence, 193 restoration completed, 194 memory copy operation,
195 Unrecoverable error occurred, 196 Diagnosis completed, 19
7 protection mode switching, 200 memory space, 201
I / O space, 202 common access space, 203 individual access space, 206 I / O space A, 207 I / O
Space B, 208 Memory space A, 209 Memory space B, 210 Common space write, 211 Individual space write, 212 Common space read, 213 Individual space read, 214 Read enable signal line, 215 Write enable signal line, 222 Driver gate signal line , 223
Memory read data signal line, 225 Flag write signal line, 226 Memory write data signal line, 228
Common space access signal, 229 individual space access signal, 230 I / O address determination circuit, 231 common space designation register, 232 individual space designation register, 23
3,234 comparison circuit, 235 common space designation register setting signal line, 236 individual space designation register signal line,
39 parity generation circuit, 240 address receiver,
241 error upper limit value register, 244 error upper limit value register setting signal line, 245 error detection circuit, 246
Error detection signal line, 247 error accumulation counter, 2
48 accumulation counter output signal line, 249 comparison circuit, 2
51 input address signal line, 253 error address output signal line, 254 selector circuit, 256 error correction signal line, 260 input / output control device, 261 duplex bus conversion adapter, 262 conversion bus signal line, 263 address driver / receiver circuit, 264 data driver/
Receiver circuit, 265 address signal line, 266 address input signal line, 267 data signal line, 268 data input signal line, 269 address parity generation circuit,
70 address parity generation / selection circuit, 271 data parity generation circuit, 272 data parity generation / selection circuit, 274 address error signal line, 275
Data error signal line, 276 address area register,
277 address area signal line, 278 comparison circuit, 279
Driver output enable signal line, 282 address area register setting signal line.

Claims (1)

Claims: 1. A processing device for performing various processes, a pair of system bus controllers connected to the processing device via a CPU bus, and a pair of system bus controllers connected to the pair of system bus controllers, respectively. And a pair of memory devices respectively connected to the pair of system buses. During a write operation in the processing device, the system bus control device simultaneously transfers data from the processing device to the pair of memory devices. In a redundant memory system in which one of the system bus controllers sends data read from a corresponding memory device to the processor during a read operation in the processing device, each system bus controller transfers data. A transfer error detecting means arranged on the path to detect an error in data being transferred; An error status register that is provided one-to-one with the error detection means and holds the result of the check by the transfer error detection means; and determines whether to permit output of data read from the memory device to the CPU bus according to the content held in the error status register. A dual memory system, comprising: a CPU bus switching circuit;