JP3746957B2 - Control method of logical partitioning system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to failure processing of an information processing apparatus, and more particularly to a control method of a logical partitioning system in tightly coupled connection.
[0002]
[Prior art]
When the information processing apparatus becomes a failure, the system operation needs to be stopped depending on the degree of the failure. There are two main reasons for stopping system operation. One is due to software. In many cases, an abnormality is detected in a specific process or job, and this process or job is a process that becomes the system core. If this happens, the system must be stopped. Since such a failure is not caused by a hardware failure, it is remedied by reviewing the cause of the failure from the viewpoint of software and executing a system restart.
[0003]
The other failure is due to hardware factors, and occurs due to a failure of the system core processor, etc., and repairs the failure generation device or reduces the failure part and restarts the system. To do.
[0004]
A large-scale information processing apparatus such as a general-purpose computer has a log function as a countermeasure against the above-mentioned software / hardware failure in order to easily analyze the content of the failure and identify the suspected component from the occurrence of the failure. The log function for countermeasures against hardware failure includes a register dump function and an execution trace function.
[0005]
It is desirable that such hardware log collection is performed as soon as possible from the time of failure occurrence. The reason is that as the contents of the register dump information and the trace information elapse from the failure occurrence point, the state changes and the accuracy as a log is lost. The simplest and most effective method for transitioning the information processing device to the fault / stop state is to connect the processors to be logged with hardware-wired fault / stop signal lines and use either processor. By activating this signal line when an abnormality is detected, the entire information processing apparatus is shifted to a fault / stop state.
[0006]
With the recent development of multiprocessor technology, information processing apparatuses that perform system operations by connecting tens to hundreds of processors to the main memory have appeared in the tightly coupled apparatus. This type of information processing apparatus employs a logical partitioning system that divides a processor group into a necessary number according to the amount of business processing and operates one operating system for each processor group. The logical division is famous for PR / SM, a trademark of IBM (International Business Machines).
[0007]
In a logical partitioning system, when a processor is connected with a single failure / stop signal line, depending on the degree of failure, the logical partition that is not required to be blocked and that is properly operated is blocked. Therefore, to improve fault tolerance in a normal logical partitioning system, configure multiple information processing devices in a hot standby configuration, and continue system operation in the standby system even if a failure spreads to the entire active system Like.
However, with the spread of information technology, the work handled by computers has diversified, and there is an increasing need to operate a plurality of operating systems even in a small-scale system composed of a single information processing apparatus. On the other hand, there is an urgent need to improve the reliability of computers as mission-critical servers such as 24-hour operation. In this sense, the reliability of the information processing device alone is not an improvement in the reliability of a hot standby configuration. Improvement in technology is regarded as important.
FIG. 7 is a block diagram showing a detailed configuration of a conventional bus control unit.
The address data register 202 is connected to the address data bus 101 in the inter-processor bus 100 and exchanges data with other processor groups and the main storage device 400. The command register 203 is connected to the address data bus 101 in the inter-processor bus 100 and stores the attribute of the main memory transaction when data is exchanged between the other processor and the main memory 400. The command decoder 204 is connected to some bit fields of the command register 203 and the address data register 202, decodes the main memory transaction, and instructs various operations of the bus control device by a read instruction / write instruction and other control instructions. . The load / store control circuit 206 is connected to other functional units of the processor that performs operations and input / outputs through the processor address data signal line 208, and controls prefetch control of instructions and data used by the processor, read / write order control, cache Control and so on. The interrupt control circuit 205 is connected to another processor and the main storage device 400 via the failure / stop signal line 102 in the inter-processor bus 100, and activates the failure / stop signal line 102 when the own processor detects a failure. . In addition, when a failure occurs in another processor, a function of shifting the own processor to a failure / stop state by detecting activation of the failure / stop signal line 102 is provided. The bus control unit and other functional units of the processor stop functioning when the stop instruction signal line 207 is activated by the interrupt control circuit 205.
[0008]
[Problems to be solved by the invention]
As described above, it is desirable that the failure of each logical partition does not spread to other partitions as much as possible under logical division. However, if the method of connecting with the fault / stop signal lines is applied to the logical partitioning system, the maximum number of fault / stop signal lines is required. In recent years, with the high integration of LSIs, the amount of gates that can be taken into LSIs is increasing at an accelerated rate. However, the actual number of signal lines between the LSI and the board or between the processor and the processor cannot be increased due to physical mounting restrictions. From this point of view as well, it is necessary to reduce the number of signal lines that are not related to normal logic, such as failure / stop signal lines.
[0009]
An object of the present invention is to connect a plurality of processors to a main storage device by tight coupling, divide this processor group into a plurality of logical partitions in advance, and allocate and operate an operating system for each logical partition. In the system, when a failure occurs, control for selectively transitioning only a specific logical partition to a failure / stop state is realized without using a dedicated signal line.
[0010]
[Means for Solving the Problems]
According to the logical partitioning system control method of the present invention, a plurality of processors are connected to the main storage device by tight coupling, the processor group is divided into a plurality of logical partitions in advance, and an operating system is allocated to each logical partition. In the logical partitioning system to be operated, a step of receiving a transaction of the main storage device, a partition number to be stopped provided in a failure stop instruction defined as one of the transactions, and a preset one for each processor belong Comparing the partition number to be The main storage device transaction is divided into a plurality of stages so that the main storage transaction does not affect a processor operating normally in a different partition. The step of combining and repeating as one bus cycle, and if the comparison result matches, if the one bus cycle is being executed, it is completed and then the processor indicated by the partition number is shifted to the fault / stop state Step to make It is characterized by consisting of.
[0011]
The logical partitioning system control method according to the present invention further includes a step of defining a broadcast partition number corresponding to all partition designations as a partition number to be stopped provided in the failure stop command, and the broadcast partition number is When the set failure stop command is received, the plurality of processors Regardless of the current bus cycle The method is characterized by comprising the steps of immediately transitioning each to a fault stop state.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0013]
As shown in FIG. 1, in the present invention, arithmetic processors 200 to 240 and input / output processors 300 to 320 are connected to the main storage device 400 in a tightly coupled manner via an interprocessor bus 100.
[0014]
The arithmetic processors 200, 210, and 220 and the input / output processor 300 constitute one processor group called partition 1, and operate one operating system for this. Further, the processor 230 and the input / output processor 310 constitute one processor group, and this is used as a partition 2 to operate an operating system different from the partition 1. Similarly, the processor 240 and the input / output processor 320 constitute one processor group, and another operating system is also operated in this partition 3. The main storage device 400 is a partition sharing device that is referred to by all arithmetic processors and input / output processors in the information processing apparatus.
[0015]
Next, a detailed configuration of the bus control unit built in the arithmetic processors 200 to 240 and the input / output processors 300 to 320 will be described with reference to FIG. Note that description of the same processing as in the prior art is omitted.
[0016]
The partition number storage register 201 is a register that holds partition numbers to which the arithmetic processors 200 to 240 and the input / output processors 300 to 320 belong. The command decoder 204 is connected to some bit fields of the command register 203 and the address data register 202, decodes the main memory transaction, and instructs various operations of the bus control device by a read command / write command and other control commands.
The load / store control circuit 206 is connected to other functional units of the processor that performs operations and input / outputs by a processor address data signal line 208, and controls prefetch control of instructions and data used by the processor, read / write order control, and cache control. Etc. In response to an instruction from the command decoder 204, the interrupt control circuit 205 performs control for shifting the own processor to a fault / stop state.
[0017]
Hereinafter, an operation in the case where a fault is detected by the arithmetic processor 210 and the other arithmetic processors 200 and 220 to 240, the input / output processors 300 to 320, and the main storage device 400 are put into a fault / stop state will be described as an example.
[0018]
In the case of an information processing apparatus that does not use the logical partitioning method, the fault / stop signal line 102 is used to shift the entire information processing apparatus to the fault / stop state by the simplest method.
[0019]
In the prior art, the interrupt control circuit 205 of the arithmetic processor 210 that has detected a fault instructs the emergency stop of the information processing apparatus using the fault / stop signal line 102. And The basic operation is that the interrupt control circuit 205 of the other processor and the main storage device receives the signal and stops the processor function using the stop instruction signal line 207.
[0020]
But with logical partitioning Na When the control is performed, for example, when the failure propagation range of the arithmetic processor 210 is closed in the partition 1 in the partition 1 constituted by the arithmetic processors 200 to 220 and the input / output processor 300 in FIG. The operation processor 230 and the input / output processor 310 in the partition 2 and the operation processor 240 and the input / output processor 320 in the partition 3 are also stopped.
[0021]
Therefore, in the present invention, a partition number storage register 201 is provided in place of the failure / stop signal line 102. When a failure occurs in the processor 210 and the operating system operating on the partition 1 needs to be blocked as a system, the processor 210 transmits a failure in the partition 1 to which the own processor belongs via the inter-processor bus 100.・ A stop command is issued.
The failure / stop instruction is defined as one of main memory transactions such as a memory read instruction and a memory write instruction, and is transferred via the address data bus 101. The failure / stop instruction has a partition number as an argument in a part of the bit field of the address / data section. The processor 210 that needs to block the partition 1 sets a command code corresponding to the failure / stop instruction in the command register 203, sets a partition number corresponding to the partition 1 in the address data register 202, and stores data in the address data bus 101. Is sent to all processors under partition 1 to notify the failure / stop command. The data sent to the interprocessor bus 100 is also propagated to all the processors in the information processing apparatus and the main memory 400.
[0022]
In the arithmetic processors 200 belonging to the same partition 1, data is fetched by the command register 203 built in the bus control unit and transferred to the command decoder 204. If the decoded main memory transaction is a failure / stop instruction, the command decoder 204 holds in advance a part of the bit field data of the address data bus 101 fetched in the address data register 202 and the partition number storage register 201. Compared with the partition number to which the own processor belongs, if they match, the interrupt control circuit 205 is instructed to stop the function of the processor by the stop instruction signal line 207.
[0023]
What should be noted at this time is that even if functions other than the bus control unit of the arithmetic processor 200 become faulty / stopped and stop the operation, the bus control unit itself does not stop immediately. The bus control unit of the arithmetic processor 200 ends the access to the inter-processor bus 100 in a state where the bus operation is normal so as not to affect other partitions 2 and 3 that are normally operated on the system. It will be in the fault / stop state for the first time after being operated. Specifically, when the load / store control circuit 206 has not completed a write operation that affects other partitions, an operation for continuing the write operation or a cache built in the processor is stored in a write-in method (write back). In this case, a copy of the data in the main memory may be held in the cache, and the operation for performing the operation of flushing the cache contents to the main memory corresponds to this. .
[0024]
On the other hand, the failure / stop instruction issued from the arithmetic processor 210 is also notified to the processors belonging to the partition 2 and the partition 3 via the inter-processor bus 100. However, in these processors, the partition number set in the partition number storage register 201 and the partition number in the address data register 202 indicated by the failure / stop instruction decoded by the command decoder 204 do not match. No operation is performed for the stop command, and the subsequent operation is continued.
[0025]
Through the operations described above, the arithmetic processors 200, 210, 220 and the input / output processor 300 belonging to the partition 1 are operated by the arithmetic processor 230 and the input / output processor 310 belonging to the partition 2, and the arithmetic processor 240 and the input / output processor 320 belonging to the partition 3. Thus, it is possible to selectively set only the section 1 to the failure / stopped state without disturbing the operation.
[0026]
The present invention also has a broadcast communication function for bringing all processors in the information processing apparatus into a fault / stop state.
[0027]
This defines the broadcast partition number corresponding to all partitions as the value of the bit field indicating the logical partition number of the address / data part specified by the argument in the failure / stop instruction, and each processor assigns the broadcast partition number. When the failure / stop command set to is received, regardless of the operating state of the inter-processor bus 100, the own processor is immediately stopped to make it immediately into the failure / stop state.
[0028]
The difference from the failure / stop state transition means limited to the one partition is that the address data fetched into the address data register 202 by decoding the failure / stop instruction by the command decoder 204 of the bus controller built in each processor. If the data of the bus 101 is a broadcast partition number corresponding to all partitions, the interrupt control circuit 205 is instructed by the stop instruction signal line 207 regardless of the value of the logical partition number storage register 201 and the processor's After instructing the stop, the bus control unit itself stops the subsequent bus control operation. Specifically, the operation of the load / store control circuit 206 is stopped at that time, and the operation is forcibly stopped even when data being read or written remains in the load / store control circuit 206.
[0029]
The reason why the broadcast section number is defined and the bus control unit itself is also brought to an emergency stop is that the failure may be present in the bus control unit itself if the failure is a problem related to the entire information processing apparatus.
[0030]
The bus control unit in FIG. 2 uses the four command codes shown in FIG. 3 as the main memory transaction. That is, a memory read instruction (command code 0), a memory write instruction (command code 1), a lock instruction (command code 2), and a failure / stop instruction (command code 3). The memory write instruction is an instruction used when the arithmetic processors 200 to 240 and the input / output processors 300 to 320 write data to the main storage device 400. The memory read instruction is an instruction used when data is read from the main storage device 400 to the arithmetic processors 200 to 240 and the input / output processors 300 to 320. The lock instruction is an instruction used when exclusive control is required between the arithmetic processors 200 to 240. The failure / stop instruction is an instruction related to the present invention, which is used when the arithmetic processors 200 to 240 and the input / output processors 300 to 320 set the partition to which the processor belongs or the entire information processing apparatus to the failure / stop state. .
[0031]
The command code is composed of 4 bits and uses 4 signal lines of the address data bus 101. The command code is extracted from the address data bus 101 by the command register 203.
[0032]
In FIG. 3, the main memory transaction uses 32 signal lines of the address data bus 101 as arguments corresponding to the command code when a command is requested. This argument is extracted from the address data bus 101 by the address data register 202. The 32 signal lines used as arguments are also used for address transmission and data transmission / reception in the memory read command and memory write command.
[0033]
For all instructions, the identification number of the instruction source processor is stored in bits 0 to 7 of the argument indicated by the address data register 202. When the instruction is a lock instruction, the argument bits 8 to 15 indicate the lock type, and when the instruction is a failure / stop instruction, the argument bits 8 to 15 are set with a partition number to be in the failure / stop state.
[0034]
The partition number of the partition to be stopped is set in the partition number setting field (bits 8 to 15) of the argument used in the failure / stop instruction. In the case of the configuration of FIG. 1, the procedure is as follows. 01 (hexadecimal number, hereinafter referred to as “H”) representing the partition 1 is stored in the partition number storage register 201 built in the bus control unit of the arithmetic processors 200 to 220 and the input / output processor 300. Is set. Similarly, 02 (H) is stored in the partition number storage register 201 of the arithmetic processor 230 and the input / output processor 310 belonging to the partition 2, and the partition number storage register 201 of the arithmetic processor 240 and the input / output processor 320 belonging to the partition 3 is stored in the partition number storage register 201. 03 (H) is set.
[0035]
When a processor belonging to the partition becomes faulty in any partition and other processors belonging to the same partition are put into a failure / stop state, the command register 203 is set to 3 (H) as the command code of the failure / stop instruction. After setting, the identification number unique to the own processor is set in bits 0 to 7 of the address data register 202, and the value of the partition to which the self belongs is preset in the partition number storage register 201 in bits 8 to 15. The main memory transaction is transmitted to the address data bus 101. When each processor receives the main memory transaction flowing through the address data bus 101 by the command register 203 and decodes the instruction by the command decoder 204, the command code of the failure / stop instruction is 3 (H). The partition number to be stopped given by bits 8 to 15 of the address data register 202 is compared with the value of the partition number setting register 201 of the own processor. When the two match, the processor that has received the failure / stop instruction shifts itself to the failure / stop state.
[0036]
On the other hand, the main storage device 400 commonly used by each partition decodes only the memory read instruction and the memory write instruction. Therefore, even if the bus control unit of the main storage device 400 receives the failure / stop command, the main storage device 400 that is the partition sharing device does not enter the failure / stop state.
[0037]
Next, the transition process to the fault / stop state of the present invention will be described. FIG. 4 is a timing diagram of one bus protocol used in explaining the present invention.
In this bus protocol, one main memory transaction is composed of eight stages. That is, a bus acquisition request stage REQ (request), a bus arbitration stage ARB (arbitration), a bus synchronization stage SYN (synchronize) address transmission stage ADR (address), a transaction cancellation stage CAN (cancel), and the first half of data 1 / There are eight transmission stages DT0 (data0), transmission stage DT1 (data1) of the latter half of the data, and detection report stage CHK (check) such as a parity error.
[0038]
Even if these stages share the same hardware resource in some cases, there is no problem in operation, so that the next transaction can be executed from the middle of one main memory transaction (pipeline structure). For example, in the stage 1 bus acquisition request REQ, arguments are stored in the address data register 202 of FIG. 2, but in the address transmission ADR in stage 4, address information for main memory access is stored in the address data register 202. In addition, since there is a time lag before the main storage device 400 prepares write or read data for the address information, the first half of the write / read data in the stage 6 data transmission DT0 after two stages In the subsequent stage 7 data transmission DT 1, the second half of the write / read data is stored in the address data register 202.
[0039]
At this time, even if the stages 1 to 4 and the stages 5 to 8 are executed in an overlapping manner, the arguments of the stage 1 stored in the address data register 202, the addresses of the stage 4 and the data of the stages 6 and 7 are addressed at the same timing. Since the data register 202 is not used, there is no problem even if the next main storage transaction starts to be executed when the stages 1 to 4 are completed. A stage that can be overlapped in this way is called a state, and a unit of state repetition is called a cycle.
[0040]
In the case of the bus protocol shown in FIG. 4, state A is REQ of stage 1 and CAN of stage 5, state B is ARB of stage 2 and DT0 of stage 6, and state C is SYN of stage 3 and DT1 of stage 7. The state D is composed of the ADR of the stage 4 and the CHK of the stage 8, and one bus cycle is formed by the four states A to D.
[0041]
FIG. 5 is a timing diagram showing a bus operation until the arithmetic processor 210 belonging to the partition 1 detects a failure and the arithmetic processor 200 belonging to the same partition 1 shifts to the failure / stop state.
[0042]
The arithmetic processor 200 is executing a memory write command to the main memory 400 according to the transaction 1. At this time, it is assumed that the arithmetic processor 210 detects a failure during the stages 1 to 4 and needs to shift the partition 1 to the failure / stop state. The arithmetic processor 210 executes a failure / stop instruction in the transaction 2 starting from the stage 5.
[0043]
When the arithmetic processor 210 makes a bus acquisition request in stage 5, it sends a command code of a failure / stop instruction and a partition number to be stopped to the address data bus 101. The arithmetic processor 200 belonging to the same partition recognizes that the instruction sent to the processor bus is a failure / stop instruction, and is the same as a result of comparison with its own partition number. The parts other than the control unit are stopped. At this time, since the bus control unit of the arithmetic processor 200 is executing the memory write instruction of the preceding main memory transaction 1, if the bus operation is stopped during the execution of the transaction, the write data of the subsequent stages 6 and 7 will be stored. It becomes indefinite and data in the main memory is corrupted.
[0044]
In the first embodiment of the present invention, after the bus operation of the arithmetic processor 200 is executed to the point where there is no influence on other partitions, the operation is performed so as to shift to the failure / stop state. Therefore, the arithmetic processor 200 executes the main memory transaction 1 up to SYN in stage 8 and shifts the bus control unit to the fault stop state for the first time. As a result, the data in the main storage device 400 is held in a normal state without causing garbled data.
[0045]
On the other hand, the arithmetic processor 230 belonging to the partition 2 intends to execute a memory read instruction in the main memory transaction 3 starting from the stage 9. The arithmetic processor 230 also decodes the failure / stop instruction requested by the arithmetic processor 210 of stage 5, which is a partition number stored as an argument of the failure / stop instruction in the address data register 202 and a logical partition of the arithmetic processor 230. Since the values in the number storage register 201 do not match, the memory read instruction is normally executed from the stage 9 without being in a failure / stop state.
[0046]
Further, even if the arithmetic processor 230 reads data from the main memory address written by the arithmetic processor 200 in the transaction 1, the transaction 1 is normally completed, so the read data of the arithmetic processor 230 is garbled. The operation of the section 2 is continued in a normal state without causing any trouble.
[0047]
The second embodiment of the present invention aims to stop all the processors in the information processing apparatus as the partition number set in the partition number setting field of the address data register 202 used as an argument of the failure / stop instruction. Defined broadcast section number. In the example shown in FIG. 3, this corresponds to the case where FF (H) is set in bits 8 to 15 in the argument of the failure / stop instruction delivered via the address data bus.
[0048]
The operation up to the failure / stop state will be described in detail. If any processor fails and the failure affects the entire information processing apparatus, the failed processor stores a failure The stop instruction command code 3 (H) is set, the identification number unique to the own processor is set in bits 0 to 7 of the address data register 202, and the FF (partition number indicating broadcast notification is set in bits 8 to 15). After setting (H), the main memory transaction is transmitted to the address data bus 101.
[0049]
On the other hand, in the processor that receives the main memory transaction, the main memory transaction flowing through the address data bus 101 is received by the command register 203, and when the command is decoded by the command decoder 204, the command code 3 (H ), The target partition number given by bits 8 to 15 of the address data register 202 is referred to. At this time, the partition number storage register 201 built in the arithmetic processors 200 to 240 and the input / output processors 300 to 320 is set in advance with the partition number to which it belongs, but the object given by the address data register 202 If the partition number is FF (H) indicating the broadcast notification, the processor is shifted to the fault / stop state without performing comparison with the value of the partition number setting register 201.
[0050]
Next, the operation of the second embodiment of the present invention will be described in detail.
[0051]
FIG. 6 illustrates a bus operation until the failure / stop state is entered when it is determined that the operation processor 210 belonging to the partition 1 detects a failure and the range in which the failure state is propagated covers the entire information processing apparatus. It is a timing chart.
[0052]
It is assumed that the arithmetic processor 200 is executing a memory write command to the main storage device 400 according to the transaction 1. At this time, it is assumed that the arithmetic processor 210 detects a failure during stages 1 to 4 and the entire information processing apparatus needs to be shifted to the failure / stop state. The arithmetic processor 210 executes a failure / stop instruction in the transaction 2 starting from the stage 5.
[0053]
When the arithmetic processor 210 makes a bus acquisition request in stage 5, it sends a command code of a failure / stop instruction and a broadcast partition number indicating all partitions to the address data bus 101. On the other hand, the arithmetic processor 200 recognizes the failure / stop instruction by fetching the instruction sent to the address data bus 101 into the command register 203 at stage 5 and decoding the instruction by the command decoder 204. At this time, when the broadcast partition number is set to the partition number to be stopped, which is fetched from the address data register 202 by the arithmetic processor 200, the entire processor including the bus control unit is immediately set in the failure / stop state. It works as much as possible.
[0054]
Referring to FIG. 6, the arithmetic processor 200 is executing the transaction cancel processing CAN in the stage 5, but has received a failure / stop command based on the broadcast partition number, and therefore sends out the first half of the subsequent stage 6 data. The functions including the bus control of the arithmetic processor 200 are stopped without executing the process DT0, the transmission process DT1 of the latter half of the stage 7 data, and the detection report process CHK such as the stage 8 parity error.
[0055]
The arithmetic processor 230 belonging to the partition 2 is also trying to execute a memory read instruction in the main memory transaction 3 starting from the stage 9, but this also decodes the failure / stop instruction in the same manner as the arithmetic processor 200 in the stage 5, Since the partition number given as the argument of the failure / stop instruction is the broadcast partition number, the function of the arithmetic processor 230 is stopped without executing the memory read instruction from the stage 9.
[0056]
In the second mode of the present invention, the status information of the bus control unit can be held at a timing three stages earlier than the first mode.
[0057]
【The invention's effect】
The first effect of the present invention is that in a logical partitioning type information processing apparatus, a mechanism for selectively shifting only a specific logical partition to a failure / stop state is reduced without using a dedicated signal line. It can be realized by a wear signal line. This is because the failure / stop instruction of the processor is defined as one of the main memory transactions instead of the signal line for instructing the failure / stop, and the failure / stop state is notified using the address data bus that the processor normally has. This is because it is possible to reduce the number of signal lines for fault / stop instructions.
[0058]
The second effect is that register information and traces useful for failure analysis can be obtained by making it possible to shift to a failure / stop state at an earlier time from the failure occurrence point when a failure relating to the entire information processing apparatus occurs. This is to prevent the destruction of information from proceeding. This is because the bus control operation is stopped by using the partition number for making a specific partition failed / stopped and the broadcast partition number for making all partitions failed / stopped as arguments of the failure / stop command. By selecting the timing.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating an embodiment of the present invention.
FIG. 2 is a detailed block diagram of a bus control unit representing an embodiment of the present invention.
FIG. 3 is an instruction system diagram of a main memory transaction representing an embodiment of the present invention.
FIG. 4 is a bus protocol timing diagram representing an embodiment of the present invention.
FIG. 5 is a timing chart showing a bus operation according to the first embodiment of this invention.
FIG. 6 is a timing chart showing a bus operation according to the second embodiment of the present invention.
FIG. 7 is a detailed block diagram of a bus control unit representing an embodiment of the prior art.
[Explanation of symbols]
100 Interprocessor bus
200, 210, 220, 230, 240 arithmetic processor
300, 310, 320 I / O processor
400 Main memory
101 Address data bus
102 Fault / stop signal line
201 Logical partition number storage register
202 Address data register
203 Command register
204 Command decoder
205 Interrupt control circuit
206 Load / store control circuit
207 Processor stop instruction signal line
208 Processor address data signal line

Claims (2)

In a logical partitioning system in which a plurality of processors are tightly coupled to a main storage device, the processor group is divided into a plurality of logical partitions in advance, and an operating system is assigned to each logical partition for operation, the main storage device A step of receiving the transaction of the above , a step of comparing the partition number to be stopped provided in the failure stop instruction defined as one of the transactions and a partition number to which the processor belongs in advance set for each processor, The main storage device transaction is divided into a plurality of stages so that the main storage device transaction does not affect a processor operating normally in a different partition. Combining and repeating as one bus cycle, and the comparison result Control logic partitioning system characterized by comprising by the steps of shifting the long execution in the one bus cycle when match after fulfilling this processor indicated by the partition number in fault-stopped state Method. A step of defining a broadcast partition number corresponding to all partition designations in a partition number to be a stop target provided in the failure stop command, and a failure stop command in which the broadcast partition number is set, 2. The method of controlling a logical partitioning system according to claim 1, further comprising the step of causing each of the plurality of processors to immediately transition each to a fault stop state regardless of a current bus cycle .

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