JPH0772869B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly, to a double comparison type data processing device in which two data processing units simultaneously execute the same operation to detect an error. Regarding

[Conventional technology]

Although there are various types of duplex comparison methods in which two data processing units execute the same processing in order to improve the data integrity of the data processing apparatus,
A typical example is COMPUTER (Volume17, Number 8,
August'84) Intel432: A VLSI Arch introduced in
There is what is called Functional Redundancy Checking shown in itecture for Fault Tolerant Computer System.

In this Intel 432 computer, two GDPs (Generalized Data Processors) with a built-in control memory are connected to the bus, one GDP is defined as a master, and the other GDP is defined as a checker, and the same operation is executed at the same time. . The GDP that became the master outputs data to the bus and becomes the GDP that became the checker.
Inputs the data output by the master GDP to the bus and compares it with its own internal data to check for errors.

[Problems to be solved by the invention]

In the data processing device adopting the above-mentioned conventional dual comparison system, although the control storage can easily detect an error by means such as parity, the data processing unit 1 and the data processing unit 1 as shown in FIG. Control memory 3 and 4 for each 2
Since the control storage is configured to have each, the control storage, which is originally single, is duplicated, and there is a drawback that the hardware price is high and the reliability is low.

Further, as shown in FIG. 6, the data processing device adopting the conventional duplexing comparison system is composed of two data processing units 1
And 2 are connected to the bus 5, the master data processing unit outputs data to the bus 5, and the checker data processing unit inputs the data output to the bus 5 to input internal data of its own data processing unit. Since the comparison check is performed only for the bus output to the outside, it may take some time before the result of the malfunction appears on the bus output.In such a case, the detection of the malfunction is delayed. There is also a drawback that it will end up.

In view of the above-mentioned point, an object of the present invention is to make the control memory single and to perform a comparison check of a read address (hereinafter referred to as a micro address) of a microprogram from the control memory in addition to a comparison check of the bus output. Accordingly, it is to provide a data processing device that is low in price, high in reliability, and quick in detecting malfunctions.

[Means for solving problems]

The data processing apparatus of the present invention is a data processing apparatus of a duplicated comparison system in which two data processing units controlled by microinstructions read from a control memory are provided and the same processing is simultaneously executed to perform an operation check. In one, a control memory, a micro address register for storing a micro address for reading a micro instruction from the control memory, an output of the micro address register for driving the control memory, and a receiver of the other data processing unit. A driver circuit having an inactive state connected to the circuit, a receiver circuit connected to receive an output of the driver circuit of the other data processing unit, an output of the receiver circuit and an output of the micro address register. To generate an error report signal when they do not match. Comparator circuit, a microinstruction register for receiving and storing a microinstruction which is the read data of the control memory, a control circuit for decoding the output of the microinstruction register to control the arithmetic circuit, and an output to the system bus. Generating circuit for generating parity for the desired data, a data-out register for temporarily storing data to be output to the system bus in which the parity is generated by the parity generating circuit, a data part of the data-out register and the system bus Two units each including a second comparison circuit for comparing the above data portion and a system bus interface unit including a third comparison circuit for comparing the parity bit of the data out register with the parity bit on the system bus. Data processing unit and one data processing unit (B) When the address is driven toward the control memory, the other data processing unit receives the micro address at which one data processing unit has driven the control memory and compares it with the micro address in its own data processing unit to check. In the case of a mismatch, the active state and the inactive state of the driver circuit are selectively instructed to output an error report signal, and the output of the comparison circuit is selectively instructed to be valid or invalid.
When one data processing unit outputs the data section and the parity bit to the system bus, the other data processing unit outputs the data section and the parity section to be output to its own system bus and the data section and the parity section on the system bus. Selectively setting the second comparison circuit and the third comparison circuit for comparison, and
And the operation mode designating means for selectively setting an error report signal to be output when a mismatch is detected in the third comparison circuit.

[Action]

In the data processing device of the present invention, the micro address register of the two data processing units stores the micro address for reading the micro instruction from the control memory, and the driver circuit having the inactive state outputs the control address with the control memory. And a receiver circuit connected to the receiver circuit of the other data processing unit, the receiver circuit connected to receive the output of the driver circuit of the other data processing unit, and the first comparison circuit to the output of the receiver circuit and the microaddress. Compares the output of the register and generates an error report signal when they do not match, the microinstruction register receives and stores the microinstruction which is the read data of the control memory, and the control circuit decodes the output of the microinstruction register and calculates It controls the circuit and controls the system bus interface. Generating circuit parity generated for the data to be output to the system bus, the data out register temporarily storing data to be output to the system bus parity generated by the parity generating circuit, a second
Of the data out register compares the data part of the data out register with the data part of the system bus, and the third comparison circuit compares the parity bit of the data out register with the parity bit of the system bus. When the operation mode designating means drives one of the data processing units toward the control memory with the micro address, the other data processing unit receives the micro address with which the one data processing unit has driven the control memory to receive its own data processing unit. Compares with the micro address in the register and selectively instructs the active state and the inactive state of the driver circuit to output an error report signal when they do not match, and selectively enables and disables the output of the comparator circuit. Instruct. In the operation mode designating means, when one data processing unit outputs the data section and the parity bit to the system bus, the other data processing unit should output to the system bus of the data section and the parity section and the system bus. The second comparison circuit and the third comparison circuit are selectively set so as to compare the data section and the parity section, and an error is reported when a mismatch is detected in the second comparison circuit and the third comparison circuit. Selectively set to output signal.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 5 is a block diagram showing a main part of a data processing device according to an embodiment of the present invention. In the data processing apparatus of this embodiment, two data processing units (EPU # 0 and EPU # are used.
1) 100 and 200 are commonly connected to the system bus 800, and are also connected to one control storage (CS) 300, respectively. The data processing device of this embodiment is different from the conventional data processing device shown in FIG.
There is one control memory 300 and two comparison data, a bus output and a micro address.

FIG. 4 is a block diagram showing the configuration of the data processing apparatus of this embodiment. This data processing device includes data processing units 100 and 200, a control memory 300, and a memory device (MMU).
400, input / output processing devices (I / O # 0 and O # 1) 500 and 600, a service processor (SVP) 700, and a system bus 800.

The data processing units 100 and 200 are devices having the same configuration for executing a program stored in the storage device 400, and a duplication comparison in which two units execute the same process (execution of instructions) while comparing each other. It is a system device.

The control memory 300 is a device that stores microprograms that control the data processing units 100 and 200.

The storage device is a device that stores a processing program, data, and the like.

The input / output processing devices 500 and 600 are the data processing unit 10
It is a device that controls data transfer between a peripheral device (not shown) and the storage device 400 in accordance with commands from 0 and 200.

The service processor 700 is a device that controls and diagnoses the operating state of the data processing device.

The system bus 800 provides a data transfer path between devices within the data processing device (e.g., corresponds to Intel's multi-bus).

FIG. 1 is a block diagram showing a control storage interface unit of the data processing units 100 and 200. The control storage interface section of the data processing units 100 and 200 is
Micro sequence control circuit (μ-SEQ) 101 and 201
And Micro Address Registers (CSA) 102 and 202
Driver circuits 103 and 203, receiver circuits 104 and 204, comparison circuits 105 and 205, and inverter circuit 1
06 and 206, AND circuits 107 and 207, microinstruction registers (CSR) 108 and 208, microinstruction decoders (DEC) 109 and 209, and arithmetic circuits (EXC) 110 and 210. .

The micro sequence control circuits 101 and 201 determine the micro address of the micro program to be read next from the control memory 300 based on the instruction by the micro instruction decoded by the micro instruction decoders 109 and 209 and the output result of the arithmetic circuits 110 and 210. It is a circuit to decide.

The micro address registers 102 and 202 are registers for temporarily storing the micro address output from the micro sequence control circuits 101 and 201.

The driver circuits 103 and 203 are ternary driver circuits having an inactive state (corresponding to the F245 chip which is generally commercially available), and the master mode designating signals MASTER1 and MASTER2 from the service processor 700 have a logic "1". When a micro address is output, the master mode designation signal
When MASTER1 and MASTER2 are logic "0", the output becomes high impedance and the control memory 300 is not driven to be inactive.

The receiver circuits 104 and 204 are the driver circuits 103 or 2
Reference numeral 03 is a circuit for receiving the micro address that drives the control memory 300.

Comparators 105 and 205 are the microaddresses and microaddress registers received by receiver circuits 104 and 204.
This is a comparison circuit for checking a match with a micro address held inside 102 and 202.

The inverter circuits 106 and 206 use the master mode designation signal.
Generates a checker mode designating signal that is the inverted signal of MASTER1 and MASTER2. In the data processing device of this embodiment, the master mode designating signals MASTER1 and MASTER2 are inverted to form the checker mode designating signal, but the service processor 700 may separately distribute the signals.

AND circuits 107 and 207 use the master mode designation signal MAST
Allows the micro-address comparison circuits in the comparison circuits 105 and 205 to be notified to the service processor 700 as the error report signal ERRROR1 or ERROR2 when the checker mode designation signal which is the inverted signal of ER1 and MASTER2 is logic "1". Circuit.

The micro instruction registers 108 and 208 are registers that receive the micro instruction read from the control memory 300 and temporarily hold it. Since the data in the control memory 300 has a parity for data guarantee, a parity check is performed in the micro instruction registers 108 and 208.

The microinstruction decoders 109 and 209 decode the microinstructions (words) stored in the microinstruction registers 108 and 208 to generate various control signals necessary for executing program instructions.

The arithmetic circuits 110 and 210 execute arithmetic operations of various instructions under the control of microinstructions.

The master mode designation signals MASTER1 and MASTER2 from the service processor 700 are exclusively notified to the two data processing units 100 and 200, and the data processing unit 100 or the data processing unit 100 to which the master mode designation signal of logical "1" is sent. 200 operates as a master that drives the control memory 300 by a micro address, and the data processing unit 200 or 100 to which the master mode designation signal of logical “0” is sent receives the micro address from the master data processing unit 100 or 200. Then, it operates as a checker for comparing and checking the internal micro address of the data processing unit 200 or 100.

Further, the error report signal ERROR1 or ERROR2 notified to the service processor 700 is output by the data processing unit 100 or 200 in which the checker mode (master mode designation signal is logic “0”) is designated as a micro address comparison result.

FIG. 2 is a block diagram showing a system bus interface section in the data processing units 100 and 200. The system bus interface section of the data processing units 100 and 200 includes parity check circuits 151 and 251.
, Parity generation circuits 152 and 252, data-in registers (DIR) 153 and 253, and data-out registers (D
OR) 154 and 254, comparison circuits 155 and 255, comparison circuits 156 and 256, AND circuits 157 and 257, AND circuits 158 and 258, OR circuits 159 and 259, driver circuits 160 and 260, and drivers. Circuits 161 and 261;
Receiver circuits 162 and 262 and receiver circuits 163 and 2
It is configured to include 63 and.

Since the data processing units 100 and 200 operate in comparison with each other, they do not have a check circuit for parity or the like inside. Therefore, in the system bus interface, it is necessary to generate parity for output data and perform parity check for input data.

The parity check circuits 151 and 251 are parity check circuits for the input data, and the signals PE0 and P0
E1 indicates a parity error signal output from the parity check circuits 151 and 251.

Parity generating circuits 152 and 252 are parity generating circuits for data to be output.

Data-in registers 153 and 253 are system bus 800
When using the data received from, it is a register that holds the data temporarily. These data-in registers 153 and 253 have 8 bits of data and 1 of parity.
A register having a capacity corresponding to bits. When the data in the data-in registers 153 and 253 is taken in, the parity is checked by the parity check circuit 15.
Checked at 1 and 251 means used.

The data out registers 154 and 254 are the system bus 80
This is a register that temporarily stores the data to be output to 0. The data-out registers 154 and 254 are registers having a capacity corresponding to 8 bits of data and 1 bit of parity in the data processing apparatus of this embodiment.

The driver circuits 160 and 260 are ternary driver circuits having an inactive state, and the data out registers 154 and 2
It consists of 8 gates corresponding to 8 bits of 54 data parts. The driver circuits 160 and 260 output the contents of the data portion of the data out registers 154 and 254 to the system bus 800 when the control signals ENDT0 and ENDT1 from the service processor 700 are logic "1", and the control signals ENDT0 and ENDT1. Is a logic "0", the output becomes high impedance, and the system bus 800 is not driven and becomes inactive.

The driver circuits 161 and 261 are ternary driver circuits having an inactive state, and each gate circuit is composed of one gate corresponding to the parity bit of the parity part of the data out registers 154 and 254. The driver circuits 161 and 261 use the control signals ENPT0 and ENPT1 from the service processor 700.
Is a logical "1", the parity bits of the parity parts of the data out registers 154 and 254 are set to the system bus 800.
Output to the system bus 800 when the control signals ENPT0 and ENPT1 are logic "0".
Is not activated.

The receiver circuits 162 and 262 are receiver circuits for the data bits of the data section of the system bus 800 and are composed of 8 gates, and receive the contents of the data section from the system bus 800.

The receiver circuits 163 and 263 are receiver circuits for the parity bits of the parity part of the system bus 800, and are configured by one gate, and receive the parity bits of the parity part from the system bus 800.

Comparing circuits 155 and 255 are the contents of the data portion of the data out registers 154 and 254 to be output to the system bus 800 and the system bus 80 received by the receiver circuits 162 and 262.
It is a comparison circuit that compares the contents of the data portion of 0.

Comparing circuits 156 and 256 are the parity bits of data out registers 154 and 254 to be output to system bus 800 and system bus 80 received by receiver circuits 163 and 263.
It is a comparison circuit that compares the parity bit on 0.

The AND circuits 157 and 257 are the data bit comparison circuits 15
An AND circuit that controls the enable or disable of the outputs of 5 and 255, and the control signal CMPD0 from the service processor 700.
Control is enabled when CMPD1 is logic "1" and disabled when logic "0".

AND circuits 158 and 258 are parity bit comparison circuits.
An AND circuit that controls the enable or disable of the 156 and 256 outputs, and the control signal CMP from the service processor 700.
Control is enabled when P0 and CMPP1 are logic "1", and disabled when logic "0".

The OR circuits 159 and 259 are OR circuits that logically OR the outputs of the AND circuits 157 and 257 and the outputs of the AND circuits 158 and 258.

The OR circuit 310 logically ORs the comparison error signal of the data processing unit 100 (output of the OR circuit 159) and the comparison error signal of the data processing unit 200 (output of the OR circuit 259) to determine which one of the data processing units. Is an OR circuit that outputs to the service processor 700 a signal CMPER that indicates that an unauthorized operation has occurred.

Each of the above control signals ENDT0, ENDT1, ENPT0, ENPT1, CMPD0, CMPD
1, CMPP0 and CMPP1 are provided from the service processor 700 as described above, and an example of a combination of the above control signals is shown in FIG.

In FIG. 3, in case 1 and case 2, one data processing unit outputs the data part to the system bus 800 and compares the internal parity bit with the parity bit of the system bus 800, and the other data processing unit performs parity. 6 is a setting example of each control signal when a method of outputting a bit to the system bus 800 and comparing the internal data part and the data part of the system bus 800 is realized. In case 3 and case 4, each data processing unit functions as a master to output the data part and the parity bit, and the other data processing unit functions as a checker to implement a method of comparing the data part and the parity bit. It is an example of a signal setting. Further, Case 5 and Case 6 are examples of setting of each control signal when the lock is released at the time of the test and diagnosis and the data processing units are operated one by one to execute the test program and the like. Case 5 is the only mode of the data processing unit 100, and case 6 is the only mode of the data processing unit 200.

Next, the operation of the data processing apparatus of this embodiment having the above configuration will be described.

Now, from the service processor 700 to the data processing unit 1
It is assumed that the master mode designation signal MASTER1 of logic "1" is sent to the control storage interface unit of 00 and the master mode designation signal MASTER2 of logic "0" is sent to the data processing unit 200. In this state, the data processing unit 100 is designated as the master and the data processing unit 200 is designated as the checker in the micro address comparison check.

Therefore, in the data processing unit 100, the driver circuit 1
03 outputs the micro address held in the micro address register 102 and enters the active state in which the control memory 300 can be driven. Further, since the checker mode designation signal of logic "0" which is the inverted signal of the master mode designation signal MASTER1 is input to the AND circuit 107, the output of the AND circuit 107 becomes logic "0" and the error report signal ERROR1 is output. It will not be done.

On the other hand, in the data processing unit 200, the driver circuit 203 becomes inactive. In addition, the master mode designation signal MASTER
Since the checker mode designating signal of logic "1" which is the inverted signal of 2 is input to the AND circuit 207, the error report signal ERROR2 can be output to the output of the AND circuit 207.

The micro address output from the driver circuit 103 along with the execution of the micro instruction is supplied to the control memory 300,
Micro instructions are read from the control memory 300, input to the micro instruction registers 108 and 208, decoded by the micro instruction decoders 109 and 209, and executed by the arithmetic circuits 110 and 210.

Meanwhile, at the same time, the micro address output from the driver circuit 103 of the data processing unit 100 is received by the receiver circuit 204 of the data processing unit 200 and compared with the micro address held in the micro address register 202 by the comparison circuit 205. To be done. Here, the micro address from the data processing unit 100 and the data processing unit 200
If it is different from the micro address in, the comparison circuit 205 detects this and sets the output to logic "1". Since the output of the inverter circuit 206 is logical "1" now, the AND circuit 207
Outputs an error report signal ERROR2 of logic "1", and the error is reported to the service processor 700.

In the description of the operation of the control storage interface section of the data processing apparatus of the present embodiment, the data processing unit 100 is the master and the data processing unit 200 is the checker in the micro address comparison check, but the master mode designating signals MASTER1 and MASTER2 are used. By inverting the logic of, the data processing unit 100 becomes a checker,
It goes without saying that the same operation is performed even if the data processing unit 200 becomes the master.

On the other hand, in the system bus interface section of the data processing units 100 and 200, the service processor 700 to the third
It is assumed that each control signal of logic as shown in case 1 of the figure is sent.

Therefore, the control signal ENDT0 becomes the logic "1" and the control signal ENDT1 becomes the logic "0", whereby the driver circuit 160 becomes the active state and the driver circuit 260 becomes the inactive state, and the data out register 154 of the data processing unit 100 The contents of the data section are output to the system bus 800, and the data processing unit 2
The contents of the data out register 254 of 00 is the system bus 800
Will not be output to.

Further, the control signal ENPT0 becomes the logic “0” and the control signal ENPT1 becomes the logic “1”, so that the driver circuit 161 is in the inactive state,
The driver circuit 261 is activated so that the parity bit of the data-out register 154 of the data processing unit 100 is not output to the system bus 800 and the parity bit of the data-out register 254 of the data processing unit 200 is output to the system bus 800. become.

Further, the control signal CMPD0 becomes the logic "0" and the control signal CMPD1 becomes the logic "1", and the AND circuit 157 is closed and the AND circuit 257 is opened, and the data processing unit 200
Data part of the data-out register 254 (system bus 1
The output of the comparison circuit 256, which compares the data portion not output to 00) and the data portion fetched from the system bus 800 (the data portion transmitted by the data processing unit 100), becomes effective.

Furthermore, the control signal CMPP0 is logic "1", and the control signal CMPP1 is
Becomes a logical "0", the AND circuit 158 is opened and the AND circuit 258 is closed, and the parity bit of the data out register 154 of the data processing unit 100 (parity bit not output to the system bus 800) is detected. The output of the comparison circuit 155, which compares the parity bit fetched from the system bus 800 (the parity bit transmitted by the data processing unit 200), becomes effective. That is,
In case 1, the data processing unit 100 outputs the data part to the system bus 800 and compares the internal parity bit with the parity bit of the system bus 800, and the data processing unit 200 outputs the parity bit to the system bus 800 and internally. Will be compared with the data part of the system bus 800.

Therefore, if one of the data processing units 100 and 200 performs an illegal operation and the data part of the data out register 154 of the data processing unit 100 and the data part of the data out register 254 of the data processing unit 200 are different, A mismatch is detected by the comparison circuit 256 of the processing unit 200, and the mismatch signal is detected by the AND circuit 257 and the OR circuit.
The service processor 700 is notified as an error report signal CMPER via the 259 and the OR circuit 310, and the error recovery processing of the data processing units 100 and 200 is performed in the service processor 700.

In the description of the operation of the system bus interface unit of the data processing apparatus according to the present embodiment, the case 1 has been described as an example. However, the operations in the other cases 2 to 6 can be easily performed from the operation in the case 1. Since it can be inferred, each case 2
Detailed description of the operation in the cases of to 6 will be omitted.

By the way, as can be understood from the explanation of the operation of the data processing device of the above embodiment, the explanation of the operation of the control storage interface unit of the data processing units 100 and 200 and the explanation of the operation of the system bus interface unit are separately explained. The operation in the control memory interface unit and the operation in the system bus interface unit are completely independent. However, in case 5 and case 6, since the data processing unit 100 and the data processing unit 200 are in the only mode, the comparison check of the micro address in the control storage interface unit is the same as the comparison check of the bus output in the system bus interface unit. It cannot be done in parallel.

〔The invention's effect〕

As described above, the present invention is carried out in a conventional data processing device by controlling two data processing units via one control memory and making a micro address comparison check in the control memory interface section. In addition to the comparison check of the bus output in the system bus interface section, it is possible to perform the comparison check of the micro address in the control memory interface section, and the low cost and high reliability data processing device can be realized by the single control memory. There is an effect that it is possible to realize a data processing apparatus that can be configured and that can detect a failure at an early timing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a control storage interface section of a data processing unit in a data processing apparatus according to an embodiment of the present invention, and FIG. 2 shows a system bus interface section of the data processing unit in the data processing apparatus of this embodiment. FIG. 3 is a block diagram, FIG. 3 is a diagram showing an example of setting various control signals in the system bus interface section shown in FIG. 2, FIG. 4 is a block diagram showing the configuration of the data processing device of this embodiment, and FIG. FIG. 6 is a block diagram showing the main part of the data processing apparatus of this embodiment, and FIG. 6 is a block diagram showing the main part of the conventional data processing apparatus. In the figure, 100,200 ... Data processing unit, 101,201 ... Micro sequence control circuit, 102,202 ... Micro address register, 103,203 ... Driver circuit, 104,204 ... Receiver circuit, 105,205 ... Comparison circuit, 106,206 ... Inverter circuit, 107,207 ...... AND circuit, 108,208 ...... micro instruction register, 109,209 ...... micro instruction decoder, 110,210 …… arithmetic circuit, 151,251 …… parity check circuit, 152,252 …… parity generation circuit, 153,253 …… data in register, 154,254 …… data Out register, 155,255 …… Comparison circuit, 156,256 …… Comparison circuit, 157,257 …… And circuit, 158,258 …… And circuit, 159,259 …… OR circuit, 160,260 …… Driver circuit, 161,261 …… Driver circuit, 162,262 …… Receiver circuit , 163,263 …… Receiver circuit, 300 …… Control memory, 310 …… OR circuit, 400 …… Memory Location, 500, 600 ...... output processing unit, 700 ...... service processor 800 ...... system bus, MASTER1, MASTER2 ...... master mode designating signal is ERROR 1, ERROR2 ...... error report signal.

Claims (1)

[Claims] 1. A data processing apparatus of a duplicated comparison system, wherein two data processing units controlled by microinstructions read from a control memory are provided and the same processing is executed at the same time to perform an operation check. Control memory of the stand, a micro address register for storing a micro address for reading a micro instruction from the control memory, and the control memory driven by the output of the micro address register and connected to the receiver circuit of the other data processing unit Comparing the output of the receiver circuit with the output of the micro-address register and a receiver circuit connected to receive the output of the driver circuit of the other data processing unit. First comparison circuit for generating an error report signal when they do not match A microinstruction register for receiving and storing a microinstruction which is the read data of the control memory, a control circuit for decoding the output of the microinstruction register to control the arithmetic circuit, and data to be output to the system bus. Generating circuit for generating parity, a data-out register for temporarily storing data to be output to the system bus in which parity is generated by the parity generating circuit, a data part of this data-out register and a data part on the system bus And a system bus interface unit including a third comparison circuit for comparing the parity bit of the data-out register with the parity bit on the system bus. And one data processing unit is a micro address When the other data processing unit receives the micro address at which one of the data processing units has driven the control memory when driving toward the control memory and compares with the micro address in its own data processing unit One of the data processing is performed by selectively instructing the active state and the inactive state of the driver circuit so as to output an error report signal and selectively instructing whether the output of the first comparison circuit is valid or invalid. When one unit outputs the data part and the parity bit to the system bus, the other data processing unit compares the data part and the parity part to be output to its own system bus with the data part and the parity part on the system bus. The second comparison circuit and the third
Operation mode designating means for selectively setting the comparator circuit of (1) and selectively outputting an error report signal when a mismatch is detected in the second comparator circuit and the third comparator circuit, A data processing device comprising: