JPS59220865A - On-line maintenance control method of dual shared memory - Google Patents

Abstract

PURPOSE:To instruct CPUs that they select a memory which is used before until it is confirmed that copying in the on-line maintenance control is performed norm rally, by providing additionally dual shared memories and an instruction for comparing both systems. CONSTITUTION:If a memory device 5 (GMB) is faulty when a CPU 1 is in the holding state and CPUs 2 and 3 perform the on-line operation, the power source is turned off. A faulty part is replaced, and the GMB is set to the maintenance mode, and GMB preferentially selecting flags of CPUs 2 and 3 are turned off, and the power source is turned on again. The CPU 1 checks the writing and the reading of all areas of a GMA; and if the check result is good, the GMB is set to the on-line mode. Contents of the GMA are copied to the GMB. All areas of the GMA and the GMB are checked with the instruction for comparing both systems by comparison; and if the check result is good, GMB preferentially selecting flags of CPUs 2 and 3 are restored. The CPU 1 protects the GMB so that on-line CPUs 2 and 3 do not use the GMB until copying is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application of the Invention The present invention relates to a duplex shared memory between a plurality of processing units.

[Background of the invention]

The overall configuration of the duplex shared memory, which is the premise of the present invention, is explained in the first section.
As shown in the figure. The memory device 4 (hereinafter abbreviated as GMA) and the memory device 5 (hereinafter abbreviated as GMB) are dual memories that store the same contents.

Number of processing devices (processing device 11 processing device 2, processing device 3
;hereinafter referred to as CPUI, CPU2. It is abbreviated as CPU3. ) are interfaces la, Ib, 2a.

Both memories are accessed via 2b, 3a, and 3b.

The access method is simultaneous writing on both systems, reading on both systems,
The read data undergoes an error check such as a parity check, and as a result, normal data is passed to the nologogram. If the read data is normal on both systems, either data, or data obtained by ORing both data, or similar composite data of both data (if the data on both systems match, the composite data also matches) ) is passed to the program.

Inno Turf A 26 between 0MA4 and 0M85 is the same - CP
In addition to being in charge of synchronization control for 0MA4 and 0MB5 to operate synchronously with respect to U accesses, 0MA4 and 0MB5
When MB5 enters duplex operation, it is in charge of copying to match the contents of 0MA4 and 0MB5.

Next, the maintenance support function of the duplex shared memory, which is the premise of the present invention, will be explained.

Suppose now that GΔ4B5 has failed. All CPUs are 0MA4
We are continuing online operation using .

Turn off the mental image of GhlB5, replace the failed part, disconnect the power supply, and start redundant operation again. However, ゛.

When you start redundant operation, if there is an abnormality in the replacement part or if there is an oversight in the replacement work, the data of GΔ4B5 will not match the data of GNiA4, and the CPU will use that incorrect data, causing the system to fail. There is a risk of it going down.

The following methods are conventionally known as methods for protecting against this danger. This method is (Special Publication No. 56-3272
0), but the summary is as follows. The CPU has means for performing maintenance-only access (hereinafter referred to as maintenance access) in addition to normal access (hereinafter referred to as online access). Which access should be used can be specified by the program. Also,
The memory device has a maintenance-only mode (hereinafter referred to as maintenance mode) in addition to a regular operation mode (hereinafter referred to as online mode). The mode can be controlled by the operator using an external switch. A memory device in online mode operates only for online access and ignores maintenance access.

A memory device in maintenance mode operates only for maintenance access and ignores online access.

Figure 2 shows the specific operational form! D. CPU2. C
PU3 is 0M in online mode with online access
Access A4, continue online work, 0MB5
is a new memory device with the faulty part replaced.The operator first put 0MB5 into maintenance mode and then
A read/write test of all memory areas is being performed using a test program at U1 maintenance access. If this test is successful, the operator switches 0MB5 to online mode. Then, 0M
Automatic copying from A4 to 0MB5 is performed, returning to the original duplex operation state.

There is one problem with the conventional technology. It finishes the test and switches from maintenance mode to online mode,
When starting duplex operation, if from 0MA4 (14B
If automatic copying to GMBS 5 is not performed normally, there is a risk that erroneous data in the GMBS will be imported into the CPU and the system will go down. However, in the past, the main purpose of duplicating shared memory was to duplicate core memory, which was less reliable than semiconductor memory, so even if it meant giving up on failures in some of the reeds and copies, there was a good point in duplicating it. However, with the recent advent of large-capacity IC memory, the proportion of hardware occupied by the memory section has become dramatically smaller, and reliability has become equivalent to that of the copy section, so failures of the copy section The situation has changed to a point where it cannot be ignored.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an online maintenance control method that confirms whether copying has been performed normally and specifies that each CPU selects the memory that it was originally using until the confirmation is completed. .

[Summary of the invention]

The present invention provides a means for changing by a program which data in the duplex memory is used for priority agreement, a means for reporting an error in one system to the program, and a means for changing the same address on both systems while occupying the shared memory. It is characterized in that each CPU is provided with a means for reading out the contents of the program and reporting it to the program.

[Embodiments of the invention]

Examples of the present invention will be described below.

FIG. 3 is a block diagram of a CPU according to an embodiment of the present invention. The arithmetic processing unit IO has a built-in memory and an instruction execution mechanism,
Processing is performed based on programs and data stored in memory. The shared memory activation control unit 7 is activated by the arithmetic processing unit 1O and sends activation information to the duplex shared memory. The shared memory response control unit 8 receives the response data from the duplex shared memory, performs a data check, and transfers the data that is considered normal to the arithmetic processing unit IO.

The single-system error freeze mechanism 9 includes a shared memory response control unit 8
This is a mechanism that stores information when a one-sided error occurs as a result of data error checking. The stored contents can be read from the arithmetic processing unit 10.

The shared memory response control unit 10 has a flag that specifies which data in the duplexed shared memory is to be used preferentially, and the flag is changed by the microprogram of the arithmetic processing unit.

The arithmetic processing unit IO implements a plurality of instructions # (addition, multiplication, branching, etc.) using a built-in microprogram. Conventionally, instructions related to the duplex shared memory include a one-sided error check instruction and a priority selection flag rewriting instruction, but in the present invention, a duplex shared memory and a double thread comparison instruction are further added.

FIG. 4 shows the instruction specifications for the two-system comparison instruction.

This instruction uses an opcode (OPC) that identifies the instruction IJ[
0DE) and three operands (OPDI.

0PD2, 0PD3). 1st Opera/C (
OPDI) specifies the GM memory address. Second
The operand stores GMA 4 data (memory address specified as 0PDI) by executing this instruction. The third operand is fiGM by executing this instruction.
The data of B5 (the memory address is specified by the same <0 PDI) is stored. However, if an error occurs in the read data of either 0MA4 or 0MB5, the result of this instruction is not guaranteed. Next, a flowchart of the microprogram of this instruction is shown in FIG. In the flowchart [
■Clear the GMB priority selection flag, but the GMB priority selection flag is a flag that determines which data in the duplex memory is used preferentially, and when it is cleared, it is 0MA.
4 is given priority, and when set, GMB5'5f: given priority. ``■Start GM reservation'' and ``Release 00M reservation.'' GM reservation means that the COU occupies the shared memory, and other CPUs have to wait for access. In this flowchart, the contents of GMA are read at ■■■, the contents of GMH are read at ■■■, and GM
The key point of this instruction is that it cannot be rewritten by another CPU because it is reserved.

FIG. 6 shows a procedure for comparing all areas of GM using this two-system comparison instruction.

``■The single-system error check command j is an instruction that reads the memory contents in the single-system error freeze mechanism 9, determines whether a single-system error has occurred, and reports the result to the program.■
determines whether the contents of both systems match, and jumps to "NO" if they do not match.

Next, a maintenance control procedure that combines the individual functions described above will be explained.

FIG. 7 is a flowchart showing one move and one stop on the maintenance opening side.

This flowchart assumes that GMB has failed and C
PU2. A case is described in which the CPU3 is in online operation, the CPU'l is on standby, and only the maintenance program is running on the CPUUI. (2) Inputs a priority selection flag rewrite command using the Conosole I10. In response to this command, O8 (operating system) rewrites this flag using a priority selection flag rewriting instruction. ■ is the content explained in FIG. @ is the same as ■. ■■■ replaces the faulty part, ■■■■ allows maintenance access
RITE, READ check, ■■■■ are used to cut without using the contents of the GM maintained by the CPU in online operation until the copy has been confirmed.

[Effects of the Invention] According to the present invention, by adding a small amount of hardware,
After checking the operation of a part of the copy during maintenance, it can be used for online operation.

[Brief explanation of the drawing]

Fig. 1 is an overall diagram of the duplex shared memory, Fig. 2 is an explanatory diagram of the maintenance support function, and Fig. 3 is a CPU of an embodiment of the present invention.
, FIG. 4 is an instruction specification diagram of the shared memory two-system comparison instruction according to an embodiment of the present invention, FIG. 5 is a microprogram flowchart of the same instruction, and FIG. 6 is a shared memory using the same instruction. Flow chart of all area comparison procedures,
FIG. 7 is a flowchart of a maintenance control procedure according to an embodiment of the present invention. 7... Shared memory start control unit, 8... Shared memory response control unit, 9... Single system error freeze mechanism, lO...
- Arithmetic processing unit. 2nd layer 3rd layer DPCDDE-: C1-IPDL/ALQpo1
: GrM ApDRESSOPD2
: GMAty+te □'-ta0PD3
: Data collection of GrMI3

Claims (1)

[Scope of Claims] 1. Consisting of a plurality of processing devices and a duplex shared memory, the duplex shared memory has means for matching the contents of both systems when duplex operation is started, and the processing device A processing method with a duplex shared memory, comprising a flag for specifying which of the data successively received from both systems of the duplex shared memory is to be used preferentially, and a means for rewriting these and the like by a program. The processing device is provided with a means for rewriting the priority designation flag in response to an external operator's request while continuing online operation, and a means for checking the consistency of the contents of both systems of the duplex shared memory, so that after maintenance of one system memory, Online maintenance control of a duplex shared memory, characterized in that the processing device in online operation preferentially uses non-maintenance side memory from the time the duplex operation is restored until the end of the consistency check of the contents of both systems. Method. 2. In claim No. 1, the processing device that checks whether the contents of both systems of the duplex shared memory match each other preferentially uses which of the data read from both systems of the duplex shared memory. A first access for reading with a flag specifying whether to do so is turned off, and a second access for reading with the flag on are performed in succession, during which the duplex shared memory is occupied, that is, 1. An online maintenance control method for a duplex resonant memory, in which a 1% chance is made to wait for another processing device to access the duplex shared memory.