JPS6386053A - Information processor - Google Patents

Abstract

PURPOSE:To easily detect that the same channel number is misused by monitoring the channel identification signal for a prescribed period of time within an input/output control register provided to another input/output controller. CONSTITUTION:An input/output controller Ar contains a bus access circuit 11, a channel number generating circuit 12, an input/output control register 13 and a bus time-out detecting circuit 14. The circuit 14 monitors the channel number for a fixed period of time within an input/output control register of another input/output controller. It is decided that a channel number is used double when the circuit 14 detects that the same channel number is stored in the input/output control register of another input/output controller.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to an information processing device, and in particular, to an information processing device and
Regarding improvement of Im structure.

(Prior Art) In an information processing device (information processing system) in which a central processing unit (CI), a main 21fi device (MMU), and a plurality of input/output control devices (<I10 controller) are connected to a common bus, Identification of the input/output control device δ is performed by a channel number provided for each input/output control device. Originally, this channel number should not be used twice, but when building a system, channel identification may be set incorrectly. If duplicate channel numbers exist in one system, two or more input/output wia will respond redundantly to accesses from the CPU. If this is the case, a situation will occur where data cannot be sent at the correct timing due to overlapping data or overlapping response signals.

(Problems to be Solved by the Invention) However, conventionally, it has been difficult to detect such overlap of signals due to the common bus structure.

The present invention has been made in consideration of the above-mentioned circumstances, and an object of the present invention is to provide an information processing device that can easily detect that the same channel number is being used erroneously.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, an information processing device according to the present invention provides access rights to the common bus to at least some input/output control devices among a plurality of input/output control devices. a bus access circuit for securing a channel identification signal, a channel identification signal generation circuit for generating a channel identification signal and outputting it to the common bus side, and a channel identification signal generation circuit for temporarily storing the channel identification signal and transmitting the channel identification signal via the bus access circuit. a bus timeout detection circuit that monitors for a predetermined period of time channel identification signals in input/output control registers connected to the common bus and input/output control registers provided in other input/output control devices other than the input/output control device; and.

(Function) In the present invention configured as described above, the bus timeout detection circuit detects other input/output υIt7I! When it is detected that the same channel number is stored in the input/output control register of the device, it is detected that the channel number is being used redundantly. By performing this detection operation, for example, at the time of system reset, it is possible to confirm whether or not the correct system configuration has been established.

(Example) Hereinafter, the present invention will be described in detail based on illustrated embodiments.

FIG. 1 shows the overall configuration of an embodiment of the present invention.

In the figure, a common bus 1 includes a central processing unit (CPU) 2, a main memory device (MMLI) 3, and a plurality of input/output υ control devices (
I10 controller) Al, A2, A3, ... An.
... is connected.

FIG. 2 shows an enlarged view of the main parts of this embodiment. In the figure, common bus 1 includes bus control $24, address/data I
! i15, command line 6, and diagnostic error! It is equipped with 27. Of these, address/data line 5 is used as a memory address line during memory access, but is also used to specify a channel when accessing the input/output control device. For example, bits 215 to 28 specify the channel number. assigned to.

The bus access circuit 11 secures the access right to the common bus 1 on the condition that the input/output v control device fimAn is in the highest priority position while the bus use request signal is issued according to the bus dialog of the common bus 1. do. Among the multiple input/output control devices AI, A2, A3, . It is.

A channel number generation circuit 12 generates a channel number for channel identification. In order to correctly identify channels, multiple input/output control devices △1, A2, A3, .
...An... must be set with different channel numbers.

Input/output control register 3 has CPtJ2 and input/output i! ,1
This is a communication area with a control device An, etc., and operation commands, addresses, lengths, etc. are set therein. Further, the channel number set in the channel number generation circuit 12 is also stored in the input/output control register 3, so that this channel number can also be read out from other input/output cars and control devices. Furthermore, bits 2 to 28 of the address/data line 5 are assigned to address the input/output control register 3, for example.

The bus timeout detection circuit 14 detects that there is no response from the accessed side even after a predetermined period of time (for example, 6 to 7 microseconds) has elapsed after accessing the common bus 1, according to the bus dialog not shown in FIG. do. That is, the third
In the figure, access to channels having the same channel number is started by the M-syn signal. If there is another input/output control I device with the same channel number set, it will respond with a 5-syn signal, which is a response signal, and in response to this response, a timeout (
-r O) Counter 1.2.3.4 is set.

Such a self-diagnosis operation is performed simultaneously on all 11 channels at the time of system reset, for example, and when an abnormal error is detected, an error flag 15 is set.
The occurrence of the error is notified to the CPU 2 and the like via the diagnostic error line 7.

The error lamp 16 is for displaying the details of the error when the error flag 15 is set.

Next, the procedure for dealing with duplicate channel numbers in this embodiment will be further explained with reference to the flowchart of FIG.

Multiple input/output control iii during system reset etc.
When all of the devices AI, A2, A3, .A n-... are initialized, each input/output control device Δ1, A2, A3, .
An... performs self-diagnosis of its own hardware.

At this stage, duplicate chitnels are also detected as described below.

The bus access circuit 11 issues a bus use request signal to the common bus 1 to obtain the right to use the common bus 1 (step 20). At this time, if there are usage requests from other input/output control devices, only the usage request of the input/output control device that is closest to the main storage device 3 in terms of implementation is selected.

At this time, bits 215 to 28 of address/data line 5
outputs the channel number as is, and outputs the channel number as is from pit 2 to 2.
It is assumed that the address specification of the input/output control register 3 of No. 8 does not matter (step 21).

Also, the command Pi16 has input/output i1. A read signal (READ command) for the lJ control register 3 is issued to change the state of other input/output control devices so that they become 1.

Note that it is necessary to close the input from the common bus 1 so that the input/output control device does not respond at this stage due to access to the common bus 1.

Next, when access to the common bus 1 is started by the M-syn signal q, the timeout counter also starts counting.

When the same channel number is duplicated, a 3-syn signal, which is a response signal, is generated, and the timeout counter is reset, so no timeout occurs. On the other hand, if the same channel number does not exist twice, there is no response from other input/output control devices, and a timeout occurs (steps 22 and 23).

When a timeout occurs, the input/output control unit 5A itself generates the 3-syn signal to cut off the M-syn signal and complete the bus dialogue.

On the other hand, when no timeout occurs, the error flag 15 is set and an error occurrence signal is output to the diagnostic error line 16. From this point on, the process is the same as when an error signal occurs during normal self-diagnosis, and the error details are displayed by the error lamp 16 (step 24.
25).

According to this embodiment, it is possible to easily detect that the same channel number is being used erroneously. Moreover,
No need to add special hardware.

In addition, the error occurs when multiple input/output pretend egg bags EA1, A
2, A3, .

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an information processing device that can easily detect that the same channel number is being used in error.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an information processing device according to an embodiment of the present invention, FIG. 2 is a block diagram showing an enlarged main part of the information processing device, and FIG. Waveform diagram without timing chart of common bus, 4th
The figure is a flowchart showing a process procedure for detecting duplicate channels in the information processing apparatus. AI, A2, A3, ... An... input/output control device,
1... Common bus, 2... Central processing unit (CPU),
3... Main 2ffi device (MMU), 4... Bus control line, 5... Address/data line, 6... Command line, 7... Diagnostic error line, 11... Bus access circuit , 12... Channel number generation circuit, 13... Input/output control register, 14... Bus timeout detection circuit, 15... Error flag, 16... Error lamp. Applicant's agent Mr. Sato Figure 1 Figure 2 Figure 4

Claims (1)

[Claims] In an information processing device that includes a plurality of input/output control devices and a common bus that connects these input/output control devices to each other,
At least some of the input/output control devices among the plurality of input/output control devices include a bus access circuit for securing access rights to the common bus, and a bus access circuit for generating a channel number for channel identification to access the common bus. an input/output control register that temporarily stores the channel number and is connected to the common bus via the bus access circuit; An information processing device comprising: a bus timeout detection circuit that monitors a channel number in an input/output control register provided in an input/output control device for a predetermined period of time.