JPS6474827A - Data converter - Google Patents

Data converter

Info

Publication number
JPS6474827A
JPS6474827A JP23332487A JP23332487A JPS6474827A JP S6474827 A JPS6474827 A JP S6474827A JP 23332487 A JP23332487 A JP 23332487A JP 23332487 A JP23332487 A JP 23332487A JP S6474827 A JPS6474827 A JP S6474827A
Authority
JP
Japan
Prior art keywords
byte
signal
circuit
data
synchronizing signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23332487A
Other languages
Japanese (ja)
Inventor
Hideaki Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP23332487A priority Critical patent/JPS6474827A/en
Publication of JPS6474827A publication Critical patent/JPS6474827A/en
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To improve an error rate, by detecting a byte synchronizing signal from serial data in which the byte synchronizing signal is inserted at every data unit with an insertion cycle almost equivalent to that of the byte synchronizing signal, and converting it to parallel data of byte unit. CONSTITUTION:The serial data SD in which the byte synchronizing signal BSC of prescribed pattern is inserted at every data unit of a prescribed quantity of information is supplied to a shift register 2. When the pattern of the parallel data outputted from the register 2 coincides with that of the signal BSC, a detection signal is outputted from a pattern detection circuit 6. However, from a pulse generation circuit 8, a pulse triggered by the detection signal and also whose pulse width TD is reduced a little than the insertion cycle Ts of the signal BSC is generated, and the synchronization of a byte synchronization counter 9 is performed by the logic output of the output signal of the circuit 8 and the detection signal of the circuit 6. In such a way, it is possible to obtain the parallel data of byte unit correctly from a latch circuit 4, thereby, to improve the error rate.
JP23332487A 1987-09-17 1987-09-17 Data converter Pending JPS6474827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23332487A JPS6474827A (en) 1987-09-17 1987-09-17 Data converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23332487A JPS6474827A (en) 1987-09-17 1987-09-17 Data converter

Publications (1)

Publication Number Publication Date
JPS6474827A true JPS6474827A (en) 1989-03-20

Family

ID=16953356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23332487A Pending JPS6474827A (en) 1987-09-17 1987-09-17 Data converter

Country Status (1)

Country Link
JP (1) JPS6474827A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02294121A (en) * 1989-05-09 1990-12-05 Nippon Hoso Kyokai <Nhk> Transmission system for parallel/serial conversion coding information signal
JP2008077124A (en) * 2006-09-19 2008-04-03 Seiko Precision Inc Interface circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02294121A (en) * 1989-05-09 1990-12-05 Nippon Hoso Kyokai <Nhk> Transmission system for parallel/serial conversion coding information signal
JP2008077124A (en) * 2006-09-19 2008-04-03 Seiko Precision Inc Interface circuit

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