SU754661A1 - Synchronisation apparatus - Google Patents

Description

The invention relates to computing and can be used to synchronize signals asynchronous with respect to the clock generator of a digital computer. five

The known synchronization devices, containing two triggers, covered by a feedback circuit, performed on the AND-NOT elements, are quite complex and, when used in unreserved U computer systems, have insufficient reliability p:].

Of the known devices, the closest in technical essence to the invention is a synchronization device comprising a storage trigger, a lock trigger, an inverter, an output matching element, the first of which is connected to the single output of the storage trigger, the second 20 input is connected to the second clock bus, and the output is connected to the output bus and connected to the single input of the blocking trigger, the input bus of the synchronized signal is connected to the input of the inverter [2},

The disadvantage of this device is the relatively low reliability due to the appearance of a false signal at the output of the device at 30

2

admission on. its input interference, able to 'change the state of the trigger.

The aim of the invention is to improve the reliability of the device.

This goal is achieved by inputting a matching element to the synchronization device, the first input of which is connected to the first bus of clock pulses, the second input is connected to the input bus of the synchronized signal, the third - to the zero output of the blocking trigger, the zero input of which is connected to the output of the inverter; the output of the input element · coincidence is connected to a single input of the storage trigger, the zero input of which is connected to the third clock bus.

Fig, 1 shows the block diagram of the device; in fig. 2 - timing diagrams explaining the operation of the device.

The device contains the first bus 1 clock pulses; input bus 2 synchronized signal; input element 3 matches; the third bus 4 clock pulses; trigger storage 5; Inverter 6; second bus 7 clock pulses; output element 8

3

754661

four

matches: trigger 9 blocking. * output bus 10ι *

The device works as follows.

The initial state of the triggers 5 and 9 is zero. If the synchronized signal on the input bus of the synchronized signal 2 and the clock pulse on the first bus of clock pulses 1 coincides, the input element of coincidence 3 is triggered, with the result that the trigger storage 5 is set to state "1". When a clock pulse arrives at the second bus clock, the output element of coincidence 8 is triggered, and a signal appears at the output bus 10, and the blocking trigger 9 is set to the state "1", locking the input element of coincidence 3 with its zero output. the third bus clock pulses 4, triggered trigger, storing 5. In this state, the device remains until the end of the synchronized signal on the input bus of the synchronized signal 2. The trigger of lock 9 is reset by a signal that appears at the output of the inverter 6 at the end of the synchronized signal on the input bus of the synchronized signal 2:

In the proposed device, the increase in reliability is achieved by gating the synchronized signal with clock pulses, the period of which is known to be longer than the maximum duration of the interference. In this case, the interference coming in the time interval, defined by the expression 1, will not cause a false signal at the output of the device.

Τ

H

Ί'Π ¹ BK *

+ 2 "

- the time interval during which the interference duration will not lead to the appearance of a false signal;

- period of clock pulses;

- the duration of the clock pulse;

- the duration of the interference;

- the minimum time required for reliable triggering.

V '

The validity of this statement clearly follows from the temporal diagram shown in FIG. 2.A

Consequently, the probability that the interference, the maximum duration of the driver, which is obviously less than the period of clock pulses, will not accept the device ^, is determined by the following expression.

P <1

s

-Έη

ten

15

20

where Ρ is the probability that the mark will not be accepted by the device- ¹ .

Thus, by an appropriate choice of the duty cycle of the clock pulses, it is possible to increase the reliability of the proposed device in order. This device can be widely used in digital computers and test equipment due to its higher reliability.

Claims (1)

Claim 25 A synchronization device containing a lock trigger, a storage trigger, an inverter, an output matching element, the first input of which is connected to the single output of the storage trigger, the second input is connected to the second clock bus, and the output is connected to the output bus and connected to the single lock trigger input , the input bus is a synchronized signal of the signal to be connected to the input of the inverter, characterized in that, in order to increase reliability, an input matching element is installed in it, the first input of which is connected to the first bus so product 40 pulses, the second input is connected to the input bus of the synchronized signal, the third one - with the ‘Zero output of the blocking trigger, the zero input of which is connected to the output of the inverter; 45, the output of the coincidence input element is connected to a single input of the storage trigger, the zero input of which is connected to the third clock bus.