RU2090971C1 - Device for discriminating first pulse out of pulse train - Google Patents

Abstract

FIELD: pulse engineering; automatic-control and measuring instruments. SUBSTANCE: device has pulse train bus 1 and RS flip-flop 7 whose R-input is connected to control bus 2, first AND gate 5, second AND gate 6, INHIBIT gate, and delay element 3; first pulse is directly discriminated from input train without clocking and at arbitrary moment of time. EFFECT: enlarged functional capabilities and improved reliability in operation. 2 dwg

Description

 The invention relates to a pulse technique and can be used in automation devices and measuring instruments.

 A device [1] is known for extracting the first pulse from a series, containing a trigger, an OR element, two And elements, and an inverter.

 The disadvantage of this device is the complexity and limited functionality of the lack of a function of subtracting the first pulse from the series.

 Closest to the invention in essence is a device [2] for synchronizing pulses containing three triggers and an NAND element, the first input of the first trigger connected to the first input of the NAND element, the second input of which is connected to the output of the first trigger, and the output element AND is NOT connected to the first input of the second trigger, an inverter, the first input of the third trigger connected to the output of the first trigger, the second input of which is connected to the output of the second trigger, the second input of which is connected to the input of the inverter, the output of which the second is connected to the third input of the AND-NOT element and to the second input of the third trigger.

 However, the known device emits a single pulse only when the pulse duration and phase coincide with the clock frequency and the asynchronous signal, i.e. for the functioning of the device requires synchronization of the latter. In addition, the disadvantage is the complexity of the hardware implementation, for example, three triggers are required, which reduces the reliability of the device as a whole.

 The purpose of the invention is the expansion of functionality and increased reliability.

 This goal is achieved by the fact that in the device for extracting the first pulse from the series, containing the RS-flip-flop, the R-input of which is connected to the control bus, the element And and the bus of the series of pulses, an additional element "Ban", a second element And and a delay element. The input of the delay element is connected to the bus of the series of pulses, with the inverse input of the element "Prohibition" and with the first inputs of the first and second elements And, and the output with the first input of the element "Prohibition". The output of the "Prohibition" element is connected to the S-input of the RS-flip-flop, the direct output of which is connected to the second input of the first element And, the inverse output to the second input of the second element I. The output of the first and second elements And are the first and second output buses, respectively.

 With such a combination of essential features, the proposed device is more reliable, since it contains only one RS-trigger memory element in its composition and has wider functionality due to the lack of synchronization between the input sequence of the pulse series and its clock cycles.

 In FIG. 1 shows a functional diagram of the device, and in FIG. 2 - time diagrams of his work.

 The proposed device contains buses of a series of pulses 1 and control 2, a delay element 3 (33 3), an element "Prohibition" 4, the first 5 and second 6 elements And, RS-flip-flop 7, the first 8 and second 9 output buses.

 A device for extracting the first pulse from the series contains an RS-trigger 7, the R-input of which is connected to the control bus 2, and the bus of the series of pulses 1, the element "Prohibition" 4, the first 5 and second 6 elements And, the delay element 3, the input of which is connected with the bus of the pulse series 1, with the inverse input of the "BAN" element 4 and with the first inputs of the first 5 and second 6 elements AND, and the output with the direct input of the element "Ban" 4, the output of which is connected to the S-input of the RS-flip-flop 7, direct the output of which is connected to the second input of the first 5 element And, the inverse output to the second input of the second about 6 element And, the output of which is the second 9 output bus, and the output of the second 5 element And is the first 8 output bus.

 The device operates as follows.

 Let a series of pulses be given (Fig. 2a) at the end of which pulses are formed (Fig. 2c). The first of the generated short pulses is the control one and switches the input series of pulses, but without the first pulse to another output bus, because a control pulse is generated at the moment of the end of the first pulse of the input pulse series.

To bring the device to its initial state, a short pulse (Fig. 2n) of duration sufficient to translate the RS-flip-flop 7 to the zero state (Fig. 2e) is supplied to the control bus 2. As a result of this, at the second inputs of the first 5 and second 6 elements And there will be potentials, respectively, logical "0" and "1". When the pulse series device 1 of the series of pulses arrives on the bus (Fig. 2a), the first pulse of the series arrives at the first input of the second 6 AND element, and since the logical input "1" is present at the second input of this I element, the first one will be generated at its output pulse input series. At the same time, a series of pulses is supplied to the inverse and through the EZ 3 to the direct input of the "Ban" element 4, the output of which is generated by a pulse (Fig. 2c) of duration t _lz sufficient to translate the RS-flip-flop 7 into a single state with the ratio t _lz <t _and , where t _lz the delay time of the EZ 3, t _lz - the delay time of the EZ 3, t _{and the} pulse duration of a series of pulses. When translating the RS-flip-flop 7 to the zero state at the inverse output, the potential of the logical unit is established (Fig. 2e). Thus, at the output of the first 5 element And a series of pulses will be formed, except for the first.

 The inventive device has wider functionality and allows you to abandon the constant synchronization between the input series of pulses and clock cycles of the device. Whereas in the prototype such a condition is fundamental. Also, the procedure for extracting the first pulse from a series in a prototype device occurs conditionally, namely only from a sequence of clock pulses, the number of which is determined by the duration of the asynchronous signal. This circumstance greatly complicates the use of the prototype device for the specific selection of the first pulse from the series. On the contrary, the claimed device performs such an operation uniquely on the input pulse sequence. In addition, the presence in its composition of only one memory element -RS-trigger, against three in the prototype, distinguishes the claimed device in terms of reliability.

Claims (1)

 A device for isolating the first pulse from the series, containing an RS-trigger, the R-input of which is connected to the control bus, the first element And and the bus of the series of pulses, characterized in that the element is BAN, the second element And and the delay element, the input of which is connected with a bus of a series of pulses, with an inverse input of the FORBID element and with the first inputs of the first and second AND elements, an output with a direct input of the FORBID element, the output of which is connected to the S-input of the RS flip-flop, the direct output of which is connected to the second input of the first AND element, inverse you stroke with the second input of the second element And, and the outputs of the first and second elements And are respectively the first and second output buses.

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