SU1661979A1 - Device for separating the first and the letter pulses in packet - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is to improve noise immunity in the presence of noise on the clock pulse bus - by introducing a single vibrator 6, the element OR 7, the elements AND 8 and 9. The device also contains D-triggers 1 and 2, elements AND 3 and 4, the control bus 12, the bus 13 clock pulses, output bus 10 and 11. 2 Il.

Description

The invention relates to a pulse technique and can be used in automation devices and computer technology.

The purpose of the invention is to increase the noise immunity in the presence of interference on the clock bus.

Figure 1 shows the electrical functional diagram of the device; figure 2 timing diagrams explaining the operation of the device.

A device for separating the first and last pulses in a packet contains the first 1 and second 2 D-flip-flops, the first 3 and second 4 elements AND-NOT, element OR NOT 5, one-shot 6, element OR 7, first 8 and second 9 elements I.

The inverse output of the first D-trigger 3 is connected to the first input of the first AND-NOT 1 element, the output of which is connected to the first output bus 10 and to the C-input of the first D-trigger 1, the direct output of which is connected to the first input of the second AND-NOT 4 element whose output is connected to the second output bus 11, the second input to the inverse output of the second D-trigger 2, the D-input of which is connected to the control bus 12, the direct output to the D-input of the first trigger 1, with the second input of the first element And NOT 3 and with the first input of the element OR NOT 5, the output of which is connected to the R-input of the first o D-flip-flop 1, the second input - with the C-input of the second D-flip-flop 2, with the third input of the first AND-NOT 3 element and with the output of the OR element 7, with the first input of the first And 8 element connected to the bus 13 clock pulses, the second the input with the control bus 12 and with the first input of the second element And 9, the second input of which through a single vibrator 6 is connected to the output of the first element And 8 and with the first input of the element OR 7. the second input of which is connected to the output of the second element And 9.

The device operates as follows.

At the initial moment (there are no pulses on the bus 12, fig.2a), the triggers 1 and 2 are in the zero state (fig.2d, c), the one-shot 6 in a single (fig.2zh). A single level from a single vibrator 6 is fed to the second input of element 9, allowing the passage of pulses from the bus 13 (Fig.2b). The pulses coming from the C-input of trigger 2 thereby confirm the zero state of the latter, and the pulses allocated to the output of element 5. confirm the zero state of trigger 1. On buses 10 and 11 there are unit levels (Fig. 2d, and).

The first pulse of the pack, arriving on bus 12 to the D-input of trigger 2, prepares it for switching. On the leading edge of the pulse from the bus 13, arriving with a certain delay in relation to the decree; the input pulse on the bus 12, the trigger 2 is switched to a single state (Fig. 2c).

At the same time, the first pulse at the input of element 8 (Fig.4e) puts the single-shot 6 in the zero state (Fig.2g). as a result, the element 9 is locked at the second input. Thus, the pulses from the bus 13 are fed to the C-input of the trigger 2 after they coincide with the burst pulses coming from the bus 12. This eliminates the possibility of interference on the bus 13 to the input of the trigger 2 (Fig.26), Element 9 remains closed to all the transit time of the burst of pulses on the bus 12 (Fig.2z).

After the pulses arrive at the D- and C-inputs of trigger 2 at the direct output of the latter, and therefore at the second input of element 3, the zero level is replaced by a single level. At the output of element 3, a zero level is formed.

The lower level of the inverted output of trigger 2, element 4 is blocked. The zero level at the output of element 3 coincides in time with the corresponding pulse on bus 13. At the end of this pulse, trigger T switches to a single state (Fig. 2C). The zero level from the inverted output of trigger 1 blocks element 3, and the single level from the direct output of trigger 1 prepares the element for switching

4. Thus, the formation of the pulse corresponding to the first pulse of the packet is completed.

Upon termination of the burst of pulses on the bus 12 at the output of element 8, the formation of pulses ceases (Fig. 2 e), and therefore, after a time τ, the one-shot 6 returns to its initial state (Fig. 2g). The time constant τ of the one-shot is set from the condition

Τ <τ <2T, where T is the pulse repetition period on bus 13.

A single level from the output of the one-shot 6 goes to the second input of element 9, thereby allowing the passage of pulses from the bus 13 to the C-input of trigger 2.

As a result of this, the leading edge of the clock pulse of trigger 2 switches to the zero state (Fig. 4c). In this case, element 3 is blocked at its second input and the operation of element 4 is allowed, at the output of which a zero level appears (Fig. 2i). Until the end of the pulse on bus 13, at the output of element 5, there continues to be a zero level 5, which goes to a single moment of termination of the pulse on bus 13. After that, trigger 1 is reset to zero (Fig. 2c!), And at the output of element 4 and on the bus 11 completes the formation of the pulse corresponding to the end of the packet of pulses on the bus 12.

Thus, the device returns to its original state and is ready to process the next burst of pulses.

As can be seen from the timing diagram of the device (Fig. 2), interference pulses on the input bus (Fig. 26) do not lead to the appearance of false pulses on the output 20 buses 10 and 11, which increases the noise immunity of the device.

Claims (1)

SUMMARY OF THE INVENTION A device for isolating the first and last pulses in a packet containing 25 first and second D-flip-flops, the inverse output of the first of which is connected to the first input of the first AND-NOT element, the output is co. which is connected to the first output bus and to the C-input of the first D-flip-flop, the direct output of which is connected to the first input of the second AND-NOT element, the output of which is connected to the second output bus, the second input - with the extra output of the second D-flip-flop, whose D-input connected to the control bus, direct output - with the D-input of the first D-trigger, with the second input of the first 10 AND-HE element and with the first input of the OR-HE element, the output of which is connected to the R-input of the first D-trigger, the second input C -input of the second D-flip-flop and with the third input of the first element AND-NOT, bus so 5 commercial pulses, characterized in that, in order to increase the noise immunity in the presence of interference on the clock bus, a single vibrator, an OR element, the first and second AND elements, the first input of the first of which is connected to the clock bus, are introduced into it, the second input - with control bus with the first input of the second element And, the second input of which is connected through a single vibrator to the output of the first element And and the first input of the OR element, the second input of which is connected to the output of the second element And, the output - with the D input of the second D-trigger. Figure 2