SU1499457A1 - Pulse sequence to square pulse converter - Google Patents

Abstract

The invention can be used in systems for processing and generating pulse signals. The purpose of the invention is to improve noise immunity. The device contains an input bus 1, a key 2, a resistor 5, a capacitor 6, a trigger 3, an output bus 7. The introduction of a trigger 4 ensures that the device does not respond to a single input pulse. 1 sec. f-ly. 2 Il.

Description

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The invention relates to ictulse technique and can be used in systems for processing and generating pulse signals, g

The purpose of the invention is to improve noise immunity.

Figure 1 shows an electrical functional diagram of the converter;

2 shows timing diagrams, c-tO to reach the reset threshold of the 1K-trigger triggering its operation,

 A pulse to a square pulse converter contains an input bus 1, a switch 2, two 15 1K triggers 3 and 4, a resistor 5, a capacitor 6 and an output bus 7, the input bus 1 connected to the control input of a switch 2 and C - inputs of flip-flops 3 and 4, direct output of flip-flop 4 20 connected to output bus 7, inverse output to its own K-input and I- input of flip-flop 3, R-input to inverse output of flip-flop 3, a, 1 - input - with direct output of trigger 3 and through res-25 resistor 5 with R-input of trigger 3, first capacitor plate 6 and information input of a switch 2, the output of which is connected to the common bus, a second capacitor plate 6 and the K-input of flip-flop 3 i30.

The converter works in the following mjiM manner.

The input of the transducer arrives at a series of pulses with frequencies F and F,, 5

where

F,

F (FIG. 2a). Duty cycle

input pulses are selected depending on the speed of the triggers and the key so that c. the moment of arrival of the impulse was carried out in the full range of capacitor 6. Let, for example, the duty cycle be 2, then when the frequency F is received

40

3, and with a certain delay in the trigger 3, the capacitor 6 begins to discharge with the same constant time through the output of the 1K flip-flop 3 (FIG. 26). After the end of the frequency pulses P, the voltage on the capacitor 6 does not have time to trigger the reset trigger trigger 3 on the R input from the frequency pulses F and at the output of the 1K flip-flop 3, the pulses disappear. The voltage of the logic 1 from the output of the 1K-flip-flop 3 by the front of the second pulse of frequency F is written to the output of the 1K-flip-flop.

4, which is kept in this state until the effect at its input of the pulse sequence of frequency F, is terminated.

A pulse train to a square pulse converter eliminates the pulse spaces in the output signal from a single pulse.

Forms from the acquisition of a pulse sequence converter into a rectangular pulse containing an output bus — an input bus connected to a control; it has a key input and a C input of the first trigger, which is connected to its R input via a resistor , the first capacitor plate and the information input of the key, the output of which is connected to the common busbar and the second module of the Converter after the impulses to the rectangle containing the output busbar, connected to the key control and the C input of cher is connected to e of the R-WMOs capacitor plate nym key input, the output is connected to the common bus

u and with the fact that, with neither noise immunity

the voltage on the capacitor 6 does not have time to reach the voltage of the srabat-a capacitor, about the trigger 3 on the R input and the trigger 3 after entering the front of the first input pulse is held by frequency pulses F b of the unit state (Fig. 2c), and after the arrival of the front of the second pulse in one state switches the trigger 4 (Fig. 2d). After the end of a series of pulses of frequency F, the voltage on the capacitor 6 reaches the response threshold of 1K trigger 3 at the R input and IK-

50

l, the second output of which is entered into it with output bus, C-input by bus, 1-input 1- from the first trigger, R-inlet output of the first three output - with its W and 1-input of the first trig connected to common

trigger 3 is reset to zero state (FIG. 2c).

At the same time, it is reset to the zero state and the trigger 4 by acting on its R-input high level from the inverse output of the trigger 3,

At each period of the frequency F, the voltage on the capacitor 6 has time

reach the reset threshold of 1K-trigger

3, and with a certain delay in the trigger 3, the capacitor 6 begins to discharge with the same constant time through the output of the 1K flip-flop 3 (FIG. 26). After the end of the frequency pulses P, the voltage on the capacitor 6 does not have time to trigger the reset trigger trigger 3 on the R input from the frequency pulses F and at the output of the 1K flip-flop 3, the pulses disappear. The voltage of the logic 1 from the output of the 1K-flip-flop 3 by the front of the second pulse of frequency F is written to the output of the 1K-flip-flop.

4, which is kept in this state until the effect at its input of the pulse sequence of frequency F, is terminated.

A pulse train to a square pulse converter eliminates the pulse spaces in the output signal from a single pulse.

Forms from the acquisition of a pulse sequence converter into a rectangular pulse containing an output bus — an input bus connected to a control; it has a key input and a C input of the first trigger, which is connected to its R input via a resistor , the first capacitor plate and the information input of the key, the output of which is connected to the common bus and the second one and so that, in order to increase the noise immunity of the capacitor transducer,

capacitor capacitor oh

l, a second trigger has been entered into it, the direct output of which is connected to the output bus, the C input is with the output bus, 1 is input 1 is with the direct output of the first trigger, R is the input with inverse output of the first trigger, and the inverse output - with its own K-input and 1-input of the first trigger, the K-input of which is connected to the common bus.

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Claims (1)

Formula from gaining A pulse sequence converter into a rectangular pulse containing an output bus is an input bus connected to the control input of the key and the C-input of the first trigger, the output of which through a resistor is connected to its R-input, the first capacitor lining and information input of the key, the output of which is connected to the common bus and the second capacitor plate, characterized in that, in order to increase the noise immunity of the converter, a second trigger is inserted into it, the direct output of which is connected to the output bus another, C-input - With an INPUT bus, 1-input - with a direct EXIT of the first trigger, R-input - with an inverse output of the first trigger, and an inverse output with its own K-input and 1-input of the first trigger, K-input which is connected to a common bus. F1 F2 F1 rLTLTLT a _y VfiOp_______________________ IT ^- TJ --- LI --- LT ^- I ................................................. .............. _; ........ r Fig 2