SU1485396A1 - Synchronous divide-by-14 frequency divider - Google Patents

Description

The invention can be used in the pulse technique for dividing the pulse repetition frequency.

The purpose of the invention is to improve the noise immunity and expand the functional capabilities of the divider by providing the ability to work without an initial installation. To do this, we introduce the element AND-NOT 6, which restores the divider when it enters the forbidden state due to the influence of interference or when the power is turned on. The divider contains triggers I 4, the element And 5, the clock bus 7.

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The invention relates to a pulse technique and can be used in devices for dividing the repetition frequency.

The purpose of the invention is to improve the noise immunity while expanding the functionality by providing the ability to work without the initial installation.

FIG. 1 shows the functional diagram of the synchronous frequency divider by 14; in fig. 2 - time diagrams of his work.

The synchronous frequency divider by 14 contains four triggers 1-4, element AND 5, element AND-NOT 6, clock bus 7. The output of element And 5 is connected to the first input of element AND-HE 6 and inputs I and K of trigger 4, the synchronization input of which connected to the clock bus 7, the second input element AND-NOT 6, synchronization inputs of the trigger 1 3 ', and the direct output of the trigger 3 is connected to the inputs I and K of the trigger 1, the inverse output of which is connected to the inputs Ki and K of the trigger 2, the forward and inverse outputs which are connected respectively with the inputs K 'and I Trig · · Gera 3, inverse output cat Oogo is connected to the first input element And 5, the second input of which is connected to the direct output of the trigger 2, while the output of the element AND-NOT 6 is connected to the inverse input To the trigger 1.

In FIG. 2 х - the sequence number of the input pulse on the clock bus 7; 5 * - signal O, At the direct output p, the first trigger 1; 6 - signal at the direct output 0 _{2 of the} second trigger 2;

H ~ signal at the direct output of the third trigger 3; $ - signal O * at the direct output (} ₄ fourth trigger 4} e - signal at the output of the NAND 6 element. The zero state of all four triggers was taken as the initial state for plotting diagrams.

The operation of the synchronous frequency divider at 14 is explained by the logical equations for the inputs of its три-flip-flops, which can be represented as follows:

1 ₄ = k, = Ι _α = k ₂ = 0 ₄ ; ι ₅ = ι ₄ = k ₄ =

where C g is the input signal on the clock bus 7.

The change in the state of 1K-flip-flops 1-4 occurs under the action of the trailing edge of the input clock according to the well-known algorithm of operation of the 1K-trigger.

Triggers 1-3 in a cycle of counting consistently pass seven states (writing from left to right): "LLC", "011", "100", "101", "001", "111", "010", (Fig. 2) .

When triggers 1–3 go to state “010”, a positive impulse * with a duration equal to the clock period is formed at the output of the element 5, which prepares the trigger 4 at the output of the element AND-NOT 6 a negative impulse with a duration equal to half the clock period (Fig, 2), which is fed to the reset input of the trigger 1. The clock signal is fed to the second input of the element AND-NOT 6 in order to eliminate the dangerous contests that occur when the triggers 1-3 transition from the state "011" to the state "100 ". Without the introduction of this connection, a short low-level impulse, resetting trigger 1, is formed on the output of the AND-NE element 6 during the transition due to the variation in the delay times of the triggering of the flip-flops 2 and 3.

During a normal counting cycle, which is a periodic repetition of seven specified states, the arrival of a reset pulse at input K of trigger 1 affects the operation of the device, since trigger 1 is already in the zero state by the time the pulse is formed. If, when the power is turned on or under the influence of random noise, the triggers 1 - 3 are set to the state "110", which is not included in the normal cycle, then the advantageous impulse of the AND-NE element 6 will set the trigger 1 to the zero state and thereby bring the device out of the false cycle. The state "110" for this divider structure represents a false cycle, since (in the absence of the newly introduced element and connections) in accordance with the operation algorithm of 1K ~ trigger, triggers 1–3 go from this state to the state "110", i.e. The state of the triggers does not change.

1485396

Claims (1)

Claim A synchronous frequency divider for 14, containing four flip-flops, element I, the output of which is connected to inputs I and K of the fourth trigger, whose outputs are outputs of the device, and the synchronization input connected to the clock bus, device input and synchronization inputs of the first, second and second the third flip-flop, and the direct output of the third flip-flop is connected to the inputs I and K of the first trigger, in * *; '., the output of which is connected to 15 inputs I and K of the second flip-flop, the forward and inverse outputs of which are connected to the inputs K and I of the third This trigger, the inverse output of which is connected to the first input of the element I, the second input of which is connected to the direct output of the second trigger, characterized in that, in order to increase noise immunity while simultaneously expanding the functionality by providing the ability to work without initial installation, an element is introduced into it AND-NOT, the output of which is connected with the inverse input K of the first trigger, and the first and second inputs are connected respectively with the output of the element AND and the clock bus. 0 12 3 4 5 6 78 9 10 11 12 13 FIG. 2