SU1667228A1 - Generator of pseudo-random pulse train - Google Patents

Abstract

The invention relates to a pulse technique and can be used in information and measurement technology. The purpose of the invention is to increase the reliability and reliability of monitoring the generated sequence — achieved by introducing modulators of adders 4 and 6 modulo two, element 5, counters 7 and 10 pulses, element 9 or 9, trigger 11, and the formation of new functional relationships provide the removal of the shift register 1 from the forbidden state and the detection of single errors in the generated sequence. The generator also contains adders 2 and 3 modulo two, a delay block 8, a bus 12 clock pulses. 1 il.

Description

The invention relates to a pulse technique and can be used in information and measurement technology.

The aim of the invention is to increase the reliability of operation and reliability of the control of the generated sequence.

The drawing shows a structural electrical circuit of the described generator.

The pseudo-random sequence generator contains the shift register 1, the corresponding outputs of which are connected to the inputs of the first adder 2 modulo two, the second adder 3 modulo two, the third adder 4 modulo two, element 5, the fourth adder 6 modulo two first counter 7 pulses block 8 delays, an OR 9 element connected in series, a second pulse counter 10 and a trigger 11, a clock bus 12, connected to the synchronization input of the second pulse counter 10 by the synchronization input of the delay block 8, a synchronization input the first counter of 7 pulses and the synchronization input of the shift register 1. Information input of the shift register 1 is connected to the first input of the third of the adder 4 modulo two by the output of the first adder 2 modulo two and the first input of the fourth adder 6 modulo two, the output of which is connected to the second input of the element OR 9 The output of the element PI 6 is connected to the second the trigger input 11, the installation input of the delay unit 8, and the VLR of the installation of the shift register 1, the corresponding outputs of which are connected to the inputs of the second adder 3 modulo two. The output of the adder 3 is connected to the information input of the block 8 ja / icp-t Ki, the stroke of which is connected to the loop of the fourth adder 6 modulo Pi

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the trigger 11 is connected to the first input element And 5, the second input of which is connected to the output of the shift register 1, the corresponding output of which is connected to the second input of the third adder 4 modulo two. The output of the adder 4 is connected to the input of the installation of the first counter of 7 pulses, the output of which is connected to the first input of the element OR 9.

The pseudo-random sequence generator works as follows.

When the generator is turned on, the first and second counters 7 and 10 pulses, delay block 8 and trigger 11 are set to the initial zero state, and shift register 1 is reset to an initial state other than zero (in the drawing, the circuits for this installation are not shown). When pulses are received from the bus of 12 clock pulses at the synchronization input of the shift register 1, it begins to form pseudo-random sequences at its outputs. The pulses from the bus 12 clock pulses also arrive at the synchronization input of the second counter 10 pulses, which, through K clocks (K-capacitance of the counter 10 pulses), sets a trigger 11 into its one state from its output, which opens AND 5 to skip the sequence from the output register 1 shift. A single signal from the output of the trigger 11 is a sign of the output of an error-free signal from the element And 5.

During generator operation, after initial setup, signals from the outputs of the corresponding bits of the shift register 1 are fed to the inputs of adders 2 and 3 modulo two. From the output of the first bit of register 1 shift, the signals arrive at the second input of the adder 4 modulo two. From the output of the adder 2 modulo two, a pseudo-randomly generated sequence of signals is fed to the information input of the shift register 1, the first input of the adder 4 modulo two and the first input of the adder 6 modulo two. To the second input of the element I 5, the sequence of signals comes from the last bit of the shift register 1. If there is an alternating sign in the generated pseudo-random sequence of signals at the output of modulator 4 modulo two, the signals that are fed to the input of the initial installation of the pulse counter 7 and continuously reset it are reset and do not allow it to overflow.

From the outputs of the corresponding bits of the shift register 1, the signals arrive at the inputs of the adder 3 modulo two. On his

the output produces a pseudo-random sequence of signals leading ahead of the sequence of signals at the output of modulator 2 modulo two by

as many ticks as needed to detect all single errors. From the output of the adder 3 modulo two sequence of signals through the block 8 of the delay is fed to the second input

adder 6 modulo two. Here a comparison is made of in-phase pseudo-random signal sequences. When error-free operation at the output of the adder 6 modulo two will produce a zero sequence of signals.

In the event of a failure in the generator or setting in the shift register 1 and the delay block 8, the state is such that at the output of the adder 6 modulo two will not

comparison, the output of the latter is a single signal. From the output of the adder 6 modulo two through the element OR 9, this signal is fed to the inputs of the initial setup of the shift register 1, the delay block 8,

the pulse counter 10 and the second input (reset) of the trigger 11. The generator is reset, and from the next clock cycle, it starts to operate correctly.

When all generator blocks are set to the states corresponding to proper operation, and the trigger 11 to the zero state, the signal from the trigger output blocks the output of a pseudo-random sequence of signals through element 5 on

generator output. However, in the absence of the initial setup signals, the pulse counter 10 cycles through a single signal at its output, therefore, the trigger 11 is automatically set to the single state as much as possible after K clocks of the pulse counter 10. As a result, the blocking is released and from this moment on the output of the generator pseudo-random sequence an unmistakable pseudo-random sequence of signals begins to be emitted.

Thus, during operation, the operation of the pseudo-random sequence generator is continuously monitored.

Claims (1)

Claims of the invention A pseudo-random sequence generator comprising a shift register, the corresponding outputs of which are connected to the inputs of the first modulo-two adder, the output of which is connected to the information input of the shift register, the corresponding outputs of which are connected to the inputs of the second modulo-two adder. a delay unit, a clock pulse bus connected to the synchronization input of the shift register, characterized in that, in order to increase the reliability and control of the generated sequence, a third modulo-two adder, the first pulse counter, the OR element, the second counter are entered into it pulses, trigger and element And, the fourth modulo two, the output of which is connected to the second input of the OR element, the output of which is connected to the second input of the trigger, the input of the installation of the delay unit and the shift register setup input, information 0 five the input of which is connected to the first input of the third modulo-two adder and the first input of the fourth modulo-two adder, the second input of which is connected to the output of the delay unit, the synchronization input of which is connected to the synchronization input of the first pulse counter, the synchronization input of the second pulse counter, and the clock pulse bus, the second input element And is connected to the output of the shift register, the corresponding output of which is connected to the second input of the third modulo two, the output of the second modulo two connectors ene to data input delay unit.