JPS5533356A - Error detection circuit - Google Patents

Error detection circuit

Info

Publication number
JPS5533356A
JPS5533356A JP10584278A JP10584278A JPS5533356A JP S5533356 A JPS5533356 A JP S5533356A JP 10584278 A JP10584278 A JP 10584278A JP 10584278 A JP10584278 A JP 10584278A JP S5533356 A JPS5533356 A JP S5533356A
Authority
JP
Japan
Prior art keywords
decoder
signal
circuit
output
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10584278A
Other languages
Japanese (ja)
Other versions
JPS6111492B2 (en
Inventor
Yasuhiro Nagayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10584278A priority Critical patent/JPS5533356A/en
Publication of JPS5533356A publication Critical patent/JPS5533356A/en
Publication of JPS6111492B2 publication Critical patent/JPS6111492B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Detection And Prevention Of Errors In Transmission (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To ensure the error detection for the decoder with a small number of the elements by providing the decoder to decode the N-bit input signal, the parity check circuit and the circuit which selects one of the output signals of the decoder based on the input signal.
CONSTITUTION: The decimal number data to be decoded is given to decoder 100 via terminals A∼C as well as to signal selection circuit 102 in the form of selection designation input signal 201. The output of decoder 100 is applied to parity check circuit 101 as well as to circuit 102 in the form of signal 206 to be selected. When the decoding state of the decoder is normal, output signals 207 and 208 of circuits 101 and 102 each feature logic 1 along with output signal 209 of NAND circuit 104 turned to logic 0 respectively, thus showing the normal state. In case the decoder produces the output at the erroneous position, signal 207 becomes 1 with signal 208 turned to 0. Thus output signal 209 features 1 to display the error of the decoder.
COPYRIGHT: (C)1980,JPO&Japio
JP10584278A 1978-08-29 1978-08-29 Error detection circuit Granted JPS5533356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10584278A JPS5533356A (en) 1978-08-29 1978-08-29 Error detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10584278A JPS5533356A (en) 1978-08-29 1978-08-29 Error detection circuit

Publications (2)

Publication Number Publication Date
JPS5533356A true JPS5533356A (en) 1980-03-08
JPS6111492B2 JPS6111492B2 (en) 1986-04-03

Family

ID=14418263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10584278A Granted JPS5533356A (en) 1978-08-29 1978-08-29 Error detection circuit

Country Status (1)

Country Link
JP (1) JPS5533356A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129855A (en) * 1982-01-27 1983-08-03 Nec Corp Deciding circuit for pulse pattern normalcy

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129855A (en) * 1982-01-27 1983-08-03 Nec Corp Deciding circuit for pulse pattern normalcy

Also Published As

Publication number Publication date
JPS6111492B2 (en) 1986-04-03

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