JPS55115757A - Fixed pattern suppression system - Google Patents
Fixed pattern suppression systemInfo
- Publication number
- JPS55115757A JPS55115757A JP2271479A JP2271479A JPS55115757A JP S55115757 A JPS55115757 A JP S55115757A JP 2271479 A JP2271479 A JP 2271479A JP 2271479 A JP2271479 A JP 2271479A JP S55115757 A JPS55115757 A JP S55115757A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- display information
- output
- given
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
Abstract
PURPOSE:To add the signal performing error correction coding to the information which shows the presence of redundant bit interruption operation to the output data and to detect the location of the display information and to decode for the error correction circuit only to the display information at the reception side. CONSTITUTION:When the data given to the input terminal 13 includes the logic ''0'' continuous in P-bit at the N frame number predetermined, the pattern detection circuit 4 outputs the signal to drive the suppression pulse generating circuit 5. The display information production circuit 8 is started at the same time with this output and the display information representing the redundant bit interruption operation is produced. Pulses are given to the suppression gate 12 from the suppression pulse generating circuit 5 to suppress the memory readout circuit drive clock 3. Further, the output signal of the circuit 5 controls the selection circuit 7 so that the output signal 6 of the logic ''1'' pattern generation circuit 6 and the memory circuit 1 can be selected. Further, the output of the circuit 7 is given to the multiplex circuit 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2271479A JPS55115757A (en) | 1979-02-28 | 1979-02-28 | Fixed pattern suppression system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2271479A JPS55115757A (en) | 1979-02-28 | 1979-02-28 | Fixed pattern suppression system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55115757A true JPS55115757A (en) | 1980-09-05 |
JPS6236418B2 JPS6236418B2 (en) | 1987-08-06 |
Family
ID=12090479
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2271479A Granted JPS55115757A (en) | 1979-02-28 | 1979-02-28 | Fixed pattern suppression system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55115757A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6428595U (en) * | 1987-08-10 | 1989-02-20 |
-
1979
- 1979-02-28 JP JP2271479A patent/JPS55115757A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6236418B2 (en) | 1987-08-06 |
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