JPS55119751A - Operation system - Google Patents

Operation system

Info

Publication number
JPS55119751A
JPS55119751A JP2749079A JP2749079A JPS55119751A JP S55119751 A JPS55119751 A JP S55119751A JP 2749079 A JP2749079 A JP 2749079A JP 2749079 A JP2749079 A JP 2749079A JP S55119751 A JPS55119751 A JP S55119751A
Authority
JP
Japan
Prior art keywords
circuit
clock
low speed
error
reduction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2749079A
Other languages
Japanese (ja)
Inventor
Fumio Hoshi
Masao Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2749079A priority Critical patent/JPS55119751A/en
Publication of JPS55119751A publication Critical patent/JPS55119751A/en
Pending legal-status Critical Current

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  • Retry When Errors Occur (AREA)

Abstract

PURPOSE: To enable remarkable contribution to the system-down time and reduction in the number of times, by selecting to low speed clock for retrial, if operation error is detected in the operation with normal clock.
CONSTITUTION: In the clock synchronism type digital operation unit, of operation error is detected in the method of parity-bit during the operation of the operation circuit 5, the error detection signal 10 is fed to the clock selection supply circuit 3 and the retrial control circuit 6. Further, the standard clock 7 from the normal clock generation circuit 1 is selected to the low speed clock 8 of the low speed clock generation circuit 2 with the circuit 3 and feeds it to the operation circuit 5, circuit 6, and error detection circuit 4. Thus, it can greatly contribute to the system down time and the reduction is the number of times.
COPYRIGHT: (C)1980,JPO&Japio
JP2749079A 1979-03-08 1979-03-08 Operation system Pending JPS55119751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2749079A JPS55119751A (en) 1979-03-08 1979-03-08 Operation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2749079A JPS55119751A (en) 1979-03-08 1979-03-08 Operation system

Publications (1)

Publication Number Publication Date
JPS55119751A true JPS55119751A (en) 1980-09-13

Family

ID=12222567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2749079A Pending JPS55119751A (en) 1979-03-08 1979-03-08 Operation system

Country Status (1)

Country Link
JP (1) JPS55119751A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05298134A (en) * 1991-12-16 1993-11-12 Internatl Business Mach Corp <Ibm> Method and mechanism for processing of processing error in computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05298134A (en) * 1991-12-16 1993-11-12 Internatl Business Mach Corp <Ibm> Method and mechanism for processing of processing error in computer system

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