JPS5717062A - Parity checking system - Google Patents
Parity checking systemInfo
- Publication number
- JPS5717062A JPS5717062A JP9085480A JP9085480A JPS5717062A JP S5717062 A JPS5717062 A JP S5717062A JP 9085480 A JP9085480 A JP 9085480A JP 9085480 A JP9085480 A JP 9085480A JP S5717062 A JPS5717062 A JP S5717062A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- parity
- bits
- information
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
PURPOSE:To ensure a highly effective transmission of information, by adapting such a system that all the bits of information comprising the data bits and parity bits can be turned into the data. CONSTITUTION:A decoding circuit 3 detects the Y field of the A-th information and then transmits the output signal if the Y field has a display of 7 for instance. This output signal is supplied to a gate circuit 4 along with the X field of the A-th information, i.e., the parity of the (A+1)th information. The circuit 4 supplies the (A+1)th parity to a parity checking circuit 5. At the same time, 8 bits of the (A+1)th information within a memory 1 are also supplied to the circuit 5 to receive a parity check with both signals. In case 7 bits of the ordinary 8 bits are used as the data with the rest 1 bit used as the parity, the circuit 3 has no actuation to give no operation to the circuit 4. Accordingly the circuit 5 reads the ordinary 7-bit data plus its parity out of the memory 1 to perform a parity check.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55090854A JPS6053889B2 (en) | 1980-07-03 | 1980-07-03 | Parity check method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55090854A JPS6053889B2 (en) | 1980-07-03 | 1980-07-03 | Parity check method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5717062A true JPS5717062A (en) | 1982-01-28 |
JPS6053889B2 JPS6053889B2 (en) | 1985-11-27 |
Family
ID=14010150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55090854A Expired JPS6053889B2 (en) | 1980-07-03 | 1980-07-03 | Parity check method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6053889B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6268997A (en) * | 1985-09-17 | 1987-03-30 | 近畿イシコ株式会社 | Upper supporter for rotary leader for pile driver, etc. |
-
1980
- 1980-07-03 JP JP55090854A patent/JPS6053889B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6053889B2 (en) | 1985-11-27 |
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