JPS54159143A - Combined circuit with parity check and parity generation - Google Patents

Combined circuit with parity check and parity generation

Info

Publication number
JPS54159143A
JPS54159143A JP6867178A JP6867178A JPS54159143A JP S54159143 A JPS54159143 A JP S54159143A JP 6867178 A JP6867178 A JP 6867178A JP 6867178 A JP6867178 A JP 6867178A JP S54159143 A JPS54159143 A JP S54159143A
Authority
JP
Japan
Prior art keywords
parity
circuit
code
data
generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6867178A
Other languages
Japanese (ja)
Inventor
Yukio Takahashi
Noboru Hagiwara
Hidehiko Kobayashi
Hiroshi Ihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6867178A priority Critical patent/JPS54159143A/en
Publication of JPS54159143A publication Critical patent/JPS54159143A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To estabilish the parity generation in common use with parity check circuit without increasing the number of gates and the number of output terminals, by constituing the latch circuit inputting the data of plurality and selection circuit and the parity generation circuit with the one integrated circuit.
CONSTITUTION: The parity code 1 and the data 2 are stored in the latch circuit 3 to output the parity code 4 and the data 5. When the selection signal 6 is in the state of 0, the code 8 of the output of the selection circuit 7 is all 0 independently of the content of the code 4 in the output of the circuit 3, and the parity generation circuit 9 inputs the data 5 from the circuit 3 and outputs the parity code 10 to the data. When the signal 6 is at state 1, the output code 8 of the circuit 7 is in agreement with the code 4 from the circuit 3, and the circuit 9 outputs the parity code 10 from the data 5 and the code 8. In this case, the code 1 is to the data 2, and the code 10 is the parity check code checking the parity of the data 5. By commonly using the output terminals at parity check and generation, the integrated circuit 11 can be obtained without increasing the number of terminals.
COPYRIGHT: (C)1979,JPO&Japio
JP6867178A 1978-06-06 1978-06-06 Combined circuit with parity check and parity generation Pending JPS54159143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6867178A JPS54159143A (en) 1978-06-06 1978-06-06 Combined circuit with parity check and parity generation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6867178A JPS54159143A (en) 1978-06-06 1978-06-06 Combined circuit with parity check and parity generation

Publications (1)

Publication Number Publication Date
JPS54159143A true JPS54159143A (en) 1979-12-15

Family

ID=13380400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6867178A Pending JPS54159143A (en) 1978-06-06 1978-06-06 Combined circuit with parity check and parity generation

Country Status (1)

Country Link
JP (1) JPS54159143A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01314338A (en) * 1988-05-26 1989-12-19 Internatl Business Mach Corp <Ibm> Buffer apparatus, transmission latch circuit and phase division circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01314338A (en) * 1988-05-26 1989-12-19 Internatl Business Mach Corp <Ibm> Buffer apparatus, transmission latch circuit and phase division circuit

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