JPH03136516A - Phase comparison circuit - Google Patents

Abstract

PURPOSE:To attain stable phase comparison against an accidental error by constituting the circuit with only two D flip-flops whose D input is always fixed to '1' or '0' and whose T input is connected respectively to 1st and 2nd terminals. CONSTITUTION:The reset of a D flip-flop 2 is always released except when the clock signal at an input terminal 10 rises. Then the output of an output terminal 20 goes always to zero at the time of rising the clock signal at an input terminal 11. Thus, the output goes to '1' only for a period of the clock at the input terminals 10, 11 from the rise to the fall automatically. Moreover, the frequent inverting operations of the output more than twice at the output terminal 20 are inhibited for a period from the rise to a succeeding rise of other input signal. When the rise of the clock signal at the input terminal 11 takes place continuously conversely, a signal of '0' is kept outputted at the output terminal 20. Thus, erroneous phase comparison due to the output inversion is evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase comparison circuit that detects a phase difference between two digital clocks, and particularly to a phase comparison circuit that can be implemented into a digital LSI.

[Conventional technology]

As a conventional phase comparator circuit that can be implemented into a digital LSI, the circuit shown in the circuit diagram of FIG. 3 is widely used.

FIG. 4 is a time chart of a conventional circuit. First, in FIG. 3, a pulse input to the input terminal 50 resets the D flip-flops 3 and 4. The data of the Q output of the D flip-flop 3 is inverted at the rising edge of the signal input to the input terminal 10, and the data of the Q output of the D flip-flop 4 is inverted at the rising edge of the signal input to the input terminal 11. It's working. A signal obtained by exclusive ORing the Q output of the D flip-flop 3 and the Q output of the D flip-flop at the gate 5 is output to the output terminal 20. This output detects the phase difference between the signal input to the input terminal 10 and the signal input to the input terminal 11.

To explain the operation of this phase difference detection using the time chart shown in FIG. A signal is output and a phase comparison is performed.

[Problem to be solved by the invention]

The conventional phase comparator circuit described above has the following two drawbacks.

(1) Under the condition that the rising pulse for resetting the D flip-flops 3 and 4 is input from the input terminal 50 only once before the clock signal at the input terminal 10 rises in order to determine the initial settings. , input terminal 10
．． The signals up to the rising edge of both clock signals of No. 11 can be used as a phase difference.

However, for example, if the reset pulse is not input from the input terminal 50, or if the timing is off, the input terminal 1
If the D flip-flops 3 and 4 are reset by the above-mentioned reset pulse before the clock signal No. 1 rises, there is a drawback that the above-mentioned required output from the output terminal 20 cannot be obtained.

(2) Next, the reason for malfunction when there is noise in the input signal to the terminal 10 will be explained with reference to the time chart of FIG.

The conditions of the input signals at the input terminals 10, 11, and 50 in FIG. 5 are the same as in the time chart in FIG. 4, except that the signal at the input terminal 10 includes a pulse due to noise, which is indicated by the arrow point A. In addition, as in the case of FIG. A pulse is generated due to the noise shown by the arrow, and the clock signal at input terminal 10 rises twice in a row before the normal rise of the clock signal at input terminal 11 reaches point B. In this case, two rises of the clock signal at the input terminal 10 cause a 0-point inversion in the signal 60, and the data in the signal at the output terminal 20 is inverted twice.
Thereafter, the length from the rise of the clock signal at the input terminal 10 to the rise of the clock signal at the input terminal 11 becomes "Oo". That is, there is a drawback that the output operation is reversed and erroneous phase comparison is performed.

[Means to solve the problem]

The phase comparator circuit of the present invention has first and second terminals that respectively input a first input signal and a second input signal,
In the phase comparator circuit comprising a third terminal that outputs a pulse corresponding to the phase difference between the first input signal and the second input signal, the D input is always fixed at 1 or 0. a first D flip-flop whose T input is connected to the first terminal; and a D flip-flop whose D input is always fixed at "1" or "Oo" and whose T input is connected to the second terminal; a second D flip-flop that is set or reset by the Q output of one of the D flip-flops; The other Q output of this second D flip-flop is connected to the third terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a time chart of the embodiment shown in the figure.

In FIG. 1, the D input of the D flip-flop 1.2 is fixed to the "l" signal. When the clock signal input to the input terminal 10 rises, the D flip-flop 1
The output 30 becomes "0" as shown in FIG. As a result, "0" is input and set to π of the D flip-flop 2, and the output terminal 20 of its Q output becomes °'l'. At this time, the Q output of the flip-flop 2 becomes "0°", and the "0°" of the signal 40 becomes π of the D flip-flop 1.
is entered and reset. Then, as shown in FIG. 2, the output 30 becomes 1''', the reset of the D flip-flop 2 is released, and the input terminal 11 enters the clock signal waiting state.Then, the clock signal of the input terminal 11 rises. Then, the Q output of the D flip-flop 2 becomes 0", and the Q output becomes 1'", and the reset of the D flip-flop 1 is released. Therefore, the output terminal 2
From 0, a signal is output that is "1'° only from the rising edge of the clock signal at the input terminal 10 to the rising edge of the clock signal at the input terminal 11.

That is, this embodiment can perform phase comparison equivalent to that of the conventional circuit.

In this embodiment, the D flip-flop 2 is always released from reset except when the clock signal at the input terminal 10 rises. Therefore, since the output of the output terminal 20 always becomes "0" at the rising edge of the clock signal of the input terminal 11, the output of the output terminal 20 is automatically set from the rising edge of the clock signal of the input terminal 10 to the output of the input terminal 11. It is determined to be '1'' only until the rising edge of the clock signal.In addition, in this embodiment, between the rising edge of one input signal and the rising edge of the next, the output of the output terminal 20 due to the rising edge of the other input signal For example, when the signal clock at the input terminal 10 rises, the D flip-flop 1 remains in the reset state until the next signal clock at the input terminal 11 rises, and during that time the input terminal It does not accept the rising edge of the signal clock of 10. Conversely, even if the rising edge of the clock of the input terminal 20 occurs continuously, a signal of 0" is output to the output terminal 20. A phase comparator circuit is obtained.

〔Effect of the invention〕

As explained above, the present invention provides a phase comparator circuit that does not require special initialization means and is stable even against accidental errors such as input signal noise by being configured with only 0,797,170,712 components. can be provided. Also, 0
It is composed of only 7,971,70,712 pieces, and has the effect of being suitable for digital LSI.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a time chart showing the operation of this embodiment, FIG. 3 is a circuit diagram of a conventional phase comparison circuit, and FIGS. The figure is a time chart showing the operation of the conventional example. 1 to 4: D flip-flop, 5: exclusive OR gate, 10.11: input terminal, 20: output terminal, 50: reset terminal.

Claims (1)

[Claims] It has first and second terminals into which a first input signal and a second input signal are respectively input, and outputs a pulse corresponding to a phase difference between the first input signal and the second input signal. a first D flip-flop whose D input is always fixed to "1" or "0" and whose T input is connected to the first terminal; is always fixed to "1" or "0", the T input is connected to the second terminal, and the second D flip-flop is set or reset by the Q output of one of the first D flip-flops. one Q output of the second D flip-flop is connected to the reset or set terminal of the first D flip-flop, and the other Q output of the second D flip-flop is connected to the third terminal. A phase comparison circuit characterized in that it is connected to.