JPH0758888B2 - Signal loss detection circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal dropout detection circuit for detecting a dropout of a signal when a dropout of the signal occurs.

[Conventional technology]

A conventional signal dropout detection circuit of this type is shown in FIG. In the figure, 1 is a sampling signal, 2 is a drop detection signal for checking the presence or absence of drop, 3 is a reset signal for initializing the circuit, 7 is a drop detection signal 2 as a clock, and its own output is data D flip-flop, 19 is an output of the D flip-flop 7, 8 is a D flip-flop using the output 19 of the D flip-flop 7 as data, and the sampling signal 1 as a clock, 20 is D
Q output of flip-flop 8. A D flip-flop 9 receives the Q output of the D flip-flop 8 and uses the sampling signal 1 as a clock. 21 is a D flip-flop 9
Q output of. 10 is an exclusive OR (EX-OR) gate which receives the Q output 20 of the D flip-flop 8 and the Q output 21 of the D flip-flop 9, and 22 is the output of the exclusive OR gate 10. 11 is exclusive or gate 10
D flip-flop whose output 22 is data and sampling signal 1 is a clock. Reference numeral 23 is an output of the D flip-flop 11, 12 is a D flip-flop having "H" level 14 as data and the output of the D flip-flop 11 is a clock, and 13 is an output signal of this circuit.

Next, the operation of the present invention will be described below with reference to the operation timing chart of the signal dropout detection circuit in FIG. First,
When the reset signal 3 changes from the "L" level to the "H" level, the D flip-flops 7, 8, 9, 11, 12 are in the data readable state. As the sampling signal 1, the sampling signal 1 having the same period as the falling detection signal 2 is input as shown in FIG. When the reset signal 3 becomes "H" level in the cycle T ₁ , the output 19 of the D flip-flop 7 becomes "H" level in the cycle T ₂ . Then, in the period T _3, when falling onto the falling detection signal 2 is generated, the output 19 in the periodic T ₃ remains unchanged at "H" level. Further, the D flip-flop 8 reads the "H" level of the output 19 by the clock pulse of the sampling signal 1 of the cycle T ₃ , and the output 20 becomes the "H" level. Then, in the cycle T ₄ , the D flip-flop 8 reads the “H” level of the output 19 by the clock pulse of the sampling signal 1, so the output 20 remains at the “H” level. Then D
The flip-flop 9 reads the "H" level of the output 20 by the clock pulse of the sampling signal 1 of the cycle T ₄ , and the output 21 becomes the "H" level. Then Ekusukurushibu OR (EX-OR) gate 10 to load output 22 and the "H" level of the output 20 and the "H" level of the output 21 in the periodic T ₄ is "L" level. Next, in cycle T ₅ , the D flip-flop 11
Reads the "L" level of the output 22 and sets the output 23 to the "H" level. In the cycle T ₅ , the D flip-flop 12 is D
Using the rising edge of the output 23 of the flip-flop 11 as a clock, "H" level data is read and "L" level is output to the output 13.

[Problems to be solved by the invention]

Since the conventional signal dropout detection circuit is configured as described above, the reset signal 3 becomes "H" level after t ₁ seconds of the sampling signal 1 as in the cycle T ₂ of the operation timing chart shown in FIG. 4, for example. If the dropout detection signal 2 is input after t ₂ seconds, the output 13 of the dropout detection circuit becomes the “L” level and the dropout detection signal 2 is detected even if the dropout detection signal 2 is not dropped. Even if the signal 2 is not dropped, there is a problem that the same result as when the drop is output is output.

The present invention has been made to solve the above problems, and even if the reset signal 3 changes from the "L" level to the "H" level at any time, the dropout detection signal 2 is not dropped. The purpose is to obtain a signal dropout detection circuit in which the output of the detection circuit becomes "L" level only when it occurs.

[Means for solving problems]

The signal dropout detection circuit according to the present invention detects the sampling signal and the dropout detection signal, and when the sampling signal precedes the dropout detection signal when the initialization signal changes, the first dropout detection signal is detected. The dropout detection signal that is output to the synchronizing means is valid, and if the dropout detection signal precedes the sampling signal, only the first dropout detection signal that is output to the synchronizing means is invalid. It is provided with a signal adjusting means.

[Work]

In the signal dropout detection circuit according to the present invention, by the dropout detection signal adjusting means for detecting the sampling signal and the dropout detection signal, when the dropout detection signal precedes the sampling signal from the time when the initialization signal changes, First
Only the first dropout detection signal output to the dropout detection signal synchronizing means is invalidated, and the dropout detection signal input by the first dropout detection signal synchronizing means is delayed from the sampling signal to prevent erroneous detection.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In the figure, the same parts as those in FIG.
In the figure, 4 is a (first) D flip-flop that outputs an "L" level output signal using the sampling signal 1 as a clock, and 5 is a set signal that is the output of the (first) D flip-flop 4. The falling detection signal 2 is used as a clock to obtain a "L" level signal at the output (second) D flip-flop 6, and the falling detection signal 2 and (the second)
No.) D-flip-flop 5 output signal is an OR gate. The (first) D flip-flop, the (second) D flip-flop 5, and the OR (OR) gate 6 constitute the falling detection signal adjusting means, and also the D flip-flop 7 and the D flip-flop. 8 constitutes the first falling detection signal synchronizing means, and the D flip-flop 9 constitutes the second falling detection signal synchronizing means.

Further, although the OR gate 6 is shown as an AND gate in negative logic in FIG. 1, it may be a positive logic OR gate.

Next, the operation of the present invention will be described with reference to the operation timing chart of FIG. First, as shown in the cycle T ₂ , when the reset signal 3 becomes “H” level after t ₁ seconds of the sampling signal 1 and the falling detection signal 2 is further input after t ₂ seconds, the (second) D flip-flop is input. The flip-flop 5 reads the "H" level data by using the falling detection signal 2 as a clock, and the output 17 of the (second) D flip-flop 5 becomes "L" level. By the way, the first D flip-flop 4 prevents the second D flip-flop 5 from operating when the dropout detection signal 2 is input before the sampling signal 1 after the reset signal 3 is input. First, after the state in which the data can be read by the input of the reset signal 3, the set signal 16 is first sent to the second D flip-flop 5 by the input of the sampling signal 1, and the second D flip-flop 5 receives the data. Make it readable. Therefore, when the drop detection signal 2 is input before the sampling signal 1 after the reset signal 3 is input to the second D flip-flop 5,
Only the first falling detection signal 2 can be invalidated.
The OR gate 6 receives the output 17 of the (second) D flip-flop 5 and the drop detection signal 2 as input, and is ORed from the cycle T _3.
The signal is output to the output 18 of the gate 6. The (third) D flip-flop 7 uses the output 18 of the OR gate 6 as a clock, and the output 19 of the (third) D flip-flop 7 becomes “H” level in the cycle T ₃ and becomes “L” in the cycle T _4. It becomes a level.

After that, the “H” level and the “L” level are repeated every cycle. The (fourth) D flip-flop 8 outputs the output 19 of the (third) D flip-flop 7 according to the sampling signal 1.
Read (fourth) output of the D flip-flop 8 will be output (synchronization object falling detection signal) 20, in the period T _2,
Reset signal 3 causes (fourth) D flip-flop 8
The output 20 is "H" in at period T ₃ levels (third) D output 19 of the flip-flop 7 is at "L" level for the output 20 is also "L" level (the fourth) D flip-flop 8 Change. After that, the output 20 repeats "H" level and "L" level every cycle. The (fifth) D flip-flop 9 receives the (fourth) D flip-flop 8 according to the sampling signal 1.
Output (20) of the (fifth) D flip-flop 9 (synchronous drop detection signal) 21 is output. The (output) 21 is set to the "L" level by the reset signal in the cycle T ₂ , and the "H" level of the output 20 is set to the (fifth) D in the cycle T _3.
Since it is read by the flip-flop 9, it becomes "H" level.
In the cycle T ₄ , the (fifth) D flip-flop 9 reads the “L” level of the output 20 and the output 21 becomes the “L” level. After that, the output 21 of the (fifth) D flip-flop 9 is the output 20
Then, the "H" level and the "L" level are repeated every cycle. The two sets of outputs 20 and 21, which are the inputs of the exclusive OR (EX-OR) gate 10, are always at opposite levels, so that the output 22 of the exclusive OR gate 10 is always at "H" level. The output 23 of the (sixth) D flip-flop 11 is at the "L" level in the cycle T ₂ by the reset signal, but is always at the "L" level because the output 22 is always at the "H" level. Therefore, the clock of the (seventh) D flip-flop 12 is not generated and the output 13 remains at the "H" level.

In the above embodiment, it was explained that the signal dropout detection circuit is operable only when the reset signal 3 is at "H" level. However, the reset terminals of the D flip-flops 4, 5, 9 and 12 are set to the positive logic, and the D flip-flop is set. If the set terminals of the flip-flops 5, 7, 8 and 11 are set to the positive logic and the output 16 of the D flip-flop 4 is taken from the Q terminal, the reset signal 3 is at "L" level and the signal dropout detection circuit It is ready for operation. Further, even if the clock input terminals of the D flip-flops 4, 5, 7, 8, 9, 11 are made negative logic, the same effect as in the above embodiment can be obtained.

〔The invention's effect〕

As described above, according to the present invention, when the sampling signal precedes the drop detection signal when the sampling signal and the drop detection signal are detected and the initialization signal changes, the first drop detection signal The dropout detection signal that is output to the synchronizing means is valid, and if the dropout detection signal precedes the sampling signal, only the first dropout detection signal that is output to the synchronizing means is invalid. Since the configuration is provided with the signal adjusting means, even if the drop detection signal precedes the sampling signal when viewed from the time when the initialization signal changes, the drop detection signal input by the first drop detection signal synchronizing means is input. Can be delayed from the sampling signal, and the signal drop detection signal can be output reliably only when the drop detection signal is dropped.

[Brief description of drawings]

1 is an overall configuration diagram of a signal dropout detection circuit according to an embodiment of the present invention, FIG. 2 is an operation timing chart of FIG. 1, FIG. 3 is an operation timing chart of a conventional signal dropout detection circuit, and FIG. Is an operation timing chart showing an example in which an erroneous output occurs in the conventional signal dropout detection circuit, and FIG. 5 is a conventional signal dropout detection circuit diagram. In the figure, 1 is a sampling signal, 2 is a drop detection signal, 3 is a reset signal, 4 is a (first) D flip-flop, 5 is a (second) D flip-flop, 6 is an OR (OR) gate, 7-9,11,12 are D flip-flops, 10
Is an EX-OR gate. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A first receiver for synchronizing a drop detection signal input from the outside with a sampling signal having the same period as the drop detection signal after a change of an initialization signal and outputting a synchronous drop detection signal. A dropout detection signal synchronizing means; and a second dropout detection signal synchronizing means for inputting the synchronous dropout detection signal and outputting the sampling signal with a delay of at least one cycle from the synchronous dropout detection signal. In the signal dropout detection circuit for detecting the dropout of the dropout detection signal input from the outside based on the synchronous dropout detection signal output from the first dropout detection signal synchronizing means and the second dropout detection signal synchronizing means, If the sampling signal precedes the drop detection signal when the sampling signal and the drop detection signal are detected and the initialization signal changes, the first drop detection signal is detected. The dropout detection signal output to the detection signal synchronizing means is valid, and when the dropout detection signal precedes the sampling signal, only the first dropout detection signal output to the first dropout detection signal synchronizing means is invalid. A signal dropout detection circuit comprising dropout detection signal adjusting means. 2. A first flip-flop that operates the drop detection signal adjusting means with a sampling signal as an input, and a second flip-flop that operates according to the drop detection signal set by the output signal of the first flip-flop. A flip-flop, a second flip-flop and an OR gate for inputting the dropout detection signal and outputting it as a new dropout detection signal to the first dropout detection signal synchronizing means are provided. The signal dropout detection circuit according to claim 1, which is characterized in that.