JPH0434790A - Fifo type memory - Google Patents

Abstract

PURPOSE:To read data without inputting a clock signal for data reading from the outside by obtaining the clock signal for data reading from the change of the reading data. CONSTITUTION:This FIFO type memory is composed of a FIFO type memory part 1 and a signal change detection part 10 detecting the change of the signal on a reading data signal line and generating a detection signal, and a control part 20 receiving the detection signal to generate a control signal performing the control and starting of a clock signal generation part 30, and a clock signal generation part 30 generating a clock signal LDCK for data reading of the FIFO type memory part 1 receiving the control signal. Thus, the clock signal for data reading from the outside is unnecessitated as an input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a FIFO type memory, particularly a FIFO type memory that does not require a clock signal for reading data and reads data only when there is a change in read data.

[Conventional technology]

As a conventional FIFO type memory, I
There is C74LS228. This FIFO type memory 1 is
a memory section 2, an input control section 3, a stack control section 4,
The data is loaded into the FIFO memory by inputting a data reading clock synchronized with the read data.

[Problem to be solved by the invention]

The above-mentioned conventional FIFO type memory output signal has a disadvantage in that it requires a clock signal for data reading that is synchronized with changes in read data and causes the data to be read into the memory.

SUMMARY OF THE INVENTION An object of the present invention is to solve such drawbacks and to provide a FIFO type memory that does not require a clock signal for reading data as an input signal.

[Means to solve the problem]

The FIFO type memory of the present invention includes: a FIF○ memory section that reads previously read data first; a signal change detection section that detects a signal change on a data signal line of the read data and generates a detection signal; The FIFO receives the control signal.
A clock signal generation section that generates a clock signal for reading data of the type memory section, and a control section that receives the detection signal and outputs the control signal of the clock signal generation section and starts it. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a partial logic circuit of an embodiment of the present invention. This figure shows a FIFO type memory unit 1, a signal change detection unit 10 that detects a signal change on a read data signal line and generates a detection signal, and a control unit that receives the detection signal and controls and starts a clock signal generation unit 30. A control unit 20 that generates a signal and an FIF that receives the control signal
The clock signal generating section 30 generates a clock signal LDCK for reading data of the O-type memory section 1.

The signal change detection section 10 includes EXOR gates 15 to 18,
It is composed of delay circuits 11 to 14 and operates using read data as an input signal. The read data input to the signal change detection unit 10 is sent to the EXOR gates 15 to 1 via one side of the EXOR gates 15 to 18 and delay circuits 11 to 14.
8 on the other side. With this, if even one read data signal line changes, that change is detected,
A pulse corresponding to the amount of delay of the delay circuits 11 to 14 is generated and outputted to the control section 20 as a detection signal.

The control unit 20 includes OR gates 25 to 28 and a delay gate 21.
24, and operates using the detection signal from the signal change detection section 10 as an input signal. The detection signal from the signal change detection unit 10 is directly connected to OR gates 25 to 28, and further connected to OR gates 25 to 28 other than the directly connected OR gates via delay circuits 21 to 24. Thereby, upon receiving the detection signal from the signal change detection section 10, a control signal for controlling and starting the clock signal generation section 30 is outputted from the OR gates 25-28.

The clock signal generation section 30 includes a D-flip-flop 31
~34 and AND gate 35. OR gate 36. It is composed of a delay gate 37 and operates using a control signal from the control section 20 as an input signal.

The control signal from the control section 20 is transmitted to the D-flip-flop 3.
Connected to clock inputs 4-34.

The D inputs of the D-flip-flops 31 to 34 are fixed at high level, and the D-flip-flops 31 to 34 have their D inputs fixed at high level.
The output of 34 is connected to AND gate 35, and its AND
The output of the gate 35 is connected to the data reading clock of the FIFO type memory section 1, and is also connected to the delay circuit 37. O
D-flip-flops 31 to 34 via R gate 36
connected to the reset input of The other side input of the OR gate 36 is the CLEA of the FIFO type memory section 1.
Input the same signal as the reset signal input to the R input.

As a result, receiving the control signal from the control section 20, D-
When the outputs of the flip-flops 31 to 34 all change to high level, the output of the AND gate 35 changes to high level, and a data read clock for the FIFO type memory section is generated. When the output of the AND gate 35 becomes high level, after the delay time of the delay circuit 37 has elapsed, the D-flip-flops 31 to 34 are reset via the OR gate 36 to prepare for the next change in the control signal, that is, the change in the read data.

Delay circuit 21 of FIFO type memory control section of this embodiment
If the read data on all the read data signal lines changes within the delay time of ~24, the change timing of the read data that changed the latest among the read data signal lines, and within the delay time of delay circuits 21 to 24. If the read data signals on all the read data signal lines do not change, all the OR gates 2
5 to 28 change to a high level, then the outputs of the D-flip-flops 31 to 34 change to a high level, and in response, the AND gate 35 changes to a high level, and the data read clock changes to the FIFO type memory section. The data is output to , and the data is read.

In other words, according to this embodiment, it is possible to obtain a clock signal for reading data from a change in read data without inputting a clock signal for reading data from the outside.

The above description describes this embodiment, and the details of the circuits such as the signal change detection section, the control section, and the clock signal generation section are not necessarily limited to this embodiment. Various things can be realized without the above.

〔Effect of the invention〕

As is clear from the above description, the FIFO type memory of the present invention has the advantage that data can be read without inputting an external clock signal for data reading.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional FIFO type memory.

1...FIFO type memory section, 2...memory section, 3.
...Input control section, 4...Stack control section, 5...8
Force control section, 10... Signal change detection section, 20... Control section, 30... Clock signal generation section, 11, 12, 13
゜14.21.22, 23, 24.37... Delay circuit, 15, 16.17.18... EXOR gate, 25
．． 26, 27, 28.36...OR gate, 31.3
2,33.34...D-flip-flop, 35...
・AND gate.

Claims (1)

[Claims] a FIFO memory section that reads the data read first;
a signal change detection section that detects a signal change on a data signal line of the read data and generates a detection signal; a clock signal generation section that receives a control signal and generates a clock signal for reading data of the FIFO type memory section; A FIFO type memory comprising: a control section that receives a detection signal, outputs the control signal for the clock signal generation section, and starts the clock signal generation section.