JPH0433407A - Latch circuit - Google Patents

Abstract

PURPOSE:To avoid generation of a spike by delaying a data input signal received at a data input control section when the generation of spike is probable, inverting completely a clock signal and entering the signal to a storage section. CONSTITUTION:When an input signal D turns from an L level to an H level just before a clock signal CLK turns from an H level to an L level, the input signal D is delayed by a buffer 9 and inputted to an OR gate 10. That is, the output D3 of the OR gate 10 is delayed by a delay time of a buffer 9 from the input signal D and inverted from L to H level, thereby retarding the inverting timing of the output D3 of the OR gate 10 from the timing of fall of the clock signal CLK sufficiently. Thus, generation of the spike is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a latch circuit built into a semiconductor integrated circuit.

[Prior Art] FIG. 5(a) is a circuit diagram showing a conventional R-S latch circuit.

This R-S latch circuit consists of two 2-man power AND gates) 51
．． 52 and two two-man powered NOR gates 53 and 54. One input terminal of the AND gates 51 and 52 is a reset terminal 71 and a set terminal 73, respectively.
It is connected to the.

Further, the other input terminals of the AND gates 51 and 52 are both connected to the clock terminal 72.

The output terminal of AND gate 51 is connected to one input terminal of NOR gate 53, and the other input terminal of this NOR gate 53 is connected to the output terminal of 'NOR gate 54. Furthermore, the output terminal of the AND gate 52 is connected to the NOR gate 5.
The other input terminal of this NOR gate 54 is connected to the output terminal of NOR gate 53. The output terminals of the NOR gates 53 and 54 are connected to an output terminal 74 and an inverting output terminal 75, respectively.

In the R-S latch circuit configured in this way, when the set signal S input to the set terminal 73 is at H level, the output signal Q output to the output terminal 74 is at H level, and the inverted output terminal Inverted output signal Q output to 75
becomes L level.

This state is maintained until the reset signal R input to the reset terminal 71 becomes H level. When the reset signal R becomes H level, the output signal Q becomes L level, and the inverted output signal Q becomes H level. Become. Note that the output signal Q
The signal inversion of the inverted output signal Q is performed in synchronization with the rise of the clock signal CLK.

In this latch circuit, an ANDNO gate and a NOR
The composite gate consisting of the gate 53 and the composite gate consisting of the ANDNO gate and the NOR gate 54 are both spike removal gates for preventing malfunction of the circuit due to spikes propagating from the reset terminal 71 or the set terminal 73.

FIG. 6(a) is a circuit diagram showing another conventional R-S latch circuit.

This R-S latch circuit consists of two two-way OR gates 51a.
+ 52a and 2 two-person NAND games) 53a, 5
4a.

This latch circuit has a reset terminal 76 and a clock terminal 77.
The basic configuration and operation are as follows:
This is similar to the latch circuit shown in the figure. In other words, Fig. 6 (a
), the OR gate 51a+52a and the NAND gates 53a and 54a respectively correspond to the AND gate 51.52 and the NOR gate 53.54 in FIG. 5(a).

This R-S latch circuit operates in the same manner as the latch circuit shown in FIG. 5(a) except that it operates with negative logic. That is, when the set signal S input to the set terminal 78 becomes L level, the output signal Q output to the output terminal 74 becomes H level.
level, and the inverted output signal Q output to the inverted output terminal 75 becomes L level. In this state, the reset terminal 76
The reset signal R input to the output signal Q is held until the reset signal R becomes L level.
is at L level, and the inverted output signal Q is at H level. In addition,
The input signal Q and the inverted output signal Q are inverted in synchronization with the falling edge of the clock signal CLK.

In this latch circuit, OR game) 51a and NAN
Composite gate consisting of D gate 53a and OR gate 5
The composite gate consisting of NAND gate 2a and NAND gate 54a is
This is a spike removal gate for preventing malfunction of the circuit due to spikes propagating from the reset terminal 76 or the set terminal 78.

Figure 7(a) shows the conventional falling edge single-phase static D
FIG. 2 is a circuit diagram showing a D latch circuit having a flip-flop configuration.

Input terminal 79 is connected to one input end of AND gate 62 and also connected to one input end of AND gate 63 via inverter 61 . The other input terminals of the AND gates 62 and 83 are both connected to the clock terminal 7.
Connected to 2.

An AND gate 62 is connected to one input terminal of the NOR gate 64.
is connected to the output terminal of the NOR gate 65, and the other input terminal is connected to the output terminal of the NOR gate 65.

Further, one input terminal of the NOR gate 65 is connected to the output terminal of the AND gate 63, and the other input terminal is connected to the NOR gate 65.
It is connected to the output terminal of the R gate 64.

The output terminal of NOR gate 64 is connected to one input terminal of OR gate 6θ, and the other input terminal of this OR gate 66 is connected to clock terminal 72. Similarly, the output terminal of NOR gate 65 is connected to one input terminal of OR gate 67, and the other input terminal of OR gate 67 is connected to clock terminal 72.

Further, one input terminal of the NAND gate 68 is connected to the output terminal of the OR gate 66, and the other input terminal of the NAND gate 68 is connected to the output terminal of the NAND gate 69. One input terminal of the NAND gate 6θ is connected to the output terminal of the OR gate 67, and the other input terminal of the NAND gate 69 is connected to the NAND gate 68.
connected to the output end of the The output terminals of the NAND gates 68 and 69 are an output terminal 74 and an inverted output terminal 7, respectively.
5.

In this D latch circuit, the signal input to the input terminal 79 is the clock signal C input to the clock terminal 72.
It is output to the output terminal 74 in synchronization with the falling edge of LK.

In this D latch circuit, each composite gate consisting of AND gates 62, 63 and NOR gates 64, 85 is a spike removal gate for preventing malfunction of the circuit due to spikes propagating from input terminal 79.

Figure 8(a) shows the conventional rising edge single-phase static D
FIG. 2 is a circuit diagram showing a D latch circuit having a flip-flop configuration.

This D latch circuit is constructed almost in the same way as the D latch circuit shown in FIG. 7(a). That is, in FIG. 8(a), OR gates 62a and 83a, 64a
+ 65 a NAND gate denoted by 66a, 8
AND gate indicated by 7a and symbol 68a + 89a
The NOR gate shown in FIG. Compatible.

This D latch circuit operates in synchronization with the rise of the clock signal CLK input to the clock terminal 72.

In this D latch circuit, OR gate 62a.

Each composite gate consisting of NAND gate 63a and NAND gate 64a+85a is a spike removal gate for preventing malfunction of the circuit due to spikes propagating from input terminal 79.

[Problem to be solved by the invention] However, in the conventional latch circuit described above,
Clock signal CLK input to spike removal gate
When the data input signal (reset signals R, R, set signals S, S, or input signal D) is inverted just before (or CLK) is inverted, a spike occurs in the output signal Q and the inverted output signal Q of the latch circuit. This spike causes a problem in that a circuit connected to the latter stage of the latch circuit malfunctions.

FIG. 5(b) is a timing chart showing the operation of the R-S latch circuit shown in FIG. 5(a).

For example, the clock signal C input to the clock terminal 72
When the set signal S input to the set terminal 73 immediately before LK is inverted from the H level to the L level is inverted from the L level to the H level, a spike is generated at the output S3 of the ANDNO gate. Since this spike passes through the NOR gate 54, a spike also occurs in the output signal Q.

FIG. 6(b) is a timing chart showing the operation of the R-8 latch circuit shown in FIG. 6(a).

For example, the clock signal C input to the clock terminal 77
When the set signal S input to the set terminal 78 is inverted from the H level to the L level immediately before LK is inverted from the L level to the H level, a spike is generated at the output S4 of the OR gate 52a. This spike is the NAND gate 54a
, a spike also occurs in the output signal Q.

FIG. 7(b) is a timing chart showing the operation of the D latch circuit shown in FIG. 7(a). For example, if the input signal CLK input to the input terminal 79 inverts from L level to H level immediately before the clock signal CLK input to clock terminal 72 inverts from H level to L level, then A
A spike occurs at the output DI of ND gate 62. This spike passes through the NOR gate 64, so the NOR
A spike also occurs at the output q of the gate 64. This spike is delayed by passing through the gate, so it passes through the flip-flop on the slave side.

That is, a spike also occurs at the output D2 of the OR gate 66, and this spike passes through the NAND gate 68, so
A spike occurs in the output signal Q.

FIG. 8(b) is a timing chart showing the operation of the D latch circuit shown in FIG. 8(a). For example, if the input signal CLK input to the input terminal 79 inverts from H level to L level immediately before the clock signal CLK input to clock terminal 72 inverts from L level to H level, then the OR
A spike occurs at the output D1 of gate 62a. This spike passes through the NAND gate 84a, so the NAND
A spike also occurs at the output q of the D gate 64a.

Then, since the spike is delayed by passing through the gate, it passes through the flip-flop on the slave side. That is, a spike also occurs in the output D2 of the AND gate 66a, and this spike passes through the NOR gate 68a, so a spike occurs in the output signal Q.

In this way, conventional latch circuits have the disadvantage that when the signal level of the data input signal is inverted just before the clock signal is inverted, a spike occurs in the output signal, which tends to cause malfunction of the subsequent circuit. There is.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a latch circuit that can avoid the occurrence of spikes due to the timing of signal inversion of a data input signal and a clock signal, and can reliably prevent malfunctions of subsequent circuits.

[Means for Solving the Problems] A latch circuit according to the present invention includes a control clock generation section that receives a clock signal and generates a control clock pulse before the level of the clock signal is inverted, and a control clock generation section that receives a data input signal. a data input control section that delays the data input signal by a time until the level of the clock signal is inverted based on the control clock pulse; and a data storage section that holds the output of the data input control section. It is characterized by

[Function] In the present invention, a control clock pulse is output from the control clock generation section before the level inversion of the rising or falling edge of the clock signal. The data input control section delays and outputs the data input signal using this control clock pulse.

In other words, as described above, a spike can occur only just before the clock signal rises or falls. Therefore, in the present invention, the data input signal input when there is a possibility that this spike occurs is delayed in the data input control section, and is input to the storage section after the clock signal is completely inverted. This makes it possible to avoid the occurrence of spikes.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1(a) is a circuit diagram showing a latch circuit according to a first embodiment of the present invention. This latch circuit is composed of a data input control section 1, a clock generation section 2, and a data storage section 3.

The clock generator 2 includes a buffer 4, a manually operated NOR gate 5, and an inverter 6. This NAN
One input end of the D gate 5 is connected to the clock terminal 21, and the other input end is connected to the clock terminal 21 via the buffer 4. And NAND gate 5
The output terminal of is connected directly and via the inverter 6 to the selection gate 7.8 of the data input control section 1.

The data input control section 1 is composed of a two-man OR gate 10, a buffer 9, and a selection gate 7.8.

One input end of the OR gate 10 is connected to an input terminal 20 via a buffer 9 and a selection gate 7. Further, the other input terminal of the OR gate 10 is connected to the input terminal 20 via the selection gate 8. The selection gate 7 is turned on and off by the output of the inverter 6 of the clock generator 2.
is turned on and off by the output of the NAND gate 5 of the clock generator 2.

The data storage section 3 is constructed in the same way as the falling edge single-phase static D flip-flop latch circuit shown in FIG. 7(a). AND gate indicated by 13,
The NOR gate denoted by 14.15, the OR gate denoted by 16.17, and the NAND gate denoted by 18.19 are the inverter denoted by 61 and the AND gate denoted by 82.83 in FIG. 7(a), respectively. , code 64.
This corresponds to a NOR gate indicated by 65, an OR gate indicated by 66.87, and a NAND gate indicated by es and ee.

FIG. 1(b) is a timing chart showing the operation of the circuit of this embodiment.

A clock signal CLK whose level is inverted at a predetermined period is input to the clock terminal 21 . This clock signal CL
K is delayed when passing through buffer 4, and is output from buffer 4 as delayed clock signal CLK2.

A clock signal CLK and a delayed clock signal CLK2 are input to the input terminal of the NAND gate 5. Therefore, N.A.
ND gate 5 outputs control clock signal CLKI, which is normally at H level and becomes L level just before clock signal CLK falls.

The input signal input to the input terminal 20 is input to the OR gate 10 via the selection gate 8 when the control clock signal CLK1 is at H level.

The data storage section 3 stores the output D3 of the OR gate 10 in synchronization with the falling edge of the clock signal CLK.

By the way, in the circuit of this embodiment, the clock signal CL
Immediately before K is inverted from the H level to the L level, the selection gate 7 is on and the selection gate 8 is off. Therefore, the clock signal CLK changes from H level to L level.
Immediately before the level is reversed, the input signal changes from the L level to the H level.
When the level is inverted, this input signal is delayed by the buffer 9 and input to the OR gate 10. In other words, O
The output D3 of the R gate 10 is output from the buffer 9 rather than the input signal.
The signal is inverted from L level to H level after a delay time of . The timing at which the output D3 of the OR gate 10 is inverted is sufficiently delayed from the timing at which the clock signal CLK falls. Therefore, no spike occurs in the output D1 of the ANDNO gate of the data storage section 3, the output q of the NOR gate 14, and the output D2 of the OR gate 16, and the output signal Q
No spikes occur either.

FIG. 2(a) is a circuit diagram showing a latch circuit according to a second embodiment of the present invention. This latch circuit also includes a data input control section 1, a clock generation section 2, and a data storage section 3. This embodiment differs from the first embodiment in that the storage section 3 is constituted by a rising edge single-phase static D flip-flop. Therefore, the data input control section 1 and the clock generation section 2 have a negative logic configuration.

The clock generator 2 is composed of one two-man powered NOR game) 5a, a buffer 4, and an inverter 6.
One input terminal of this NOR game) 5a is the clock terminal 2.
1, and the other input terminal is connected to the clock terminal 21 via the buffer 4. Further, the output of this NOR gate 5a is directly connected to the selection gate 8 of the data input control section 1, and is also connected to the selection gate 7 of the data input control section 1 via the inverter 6.

The data input control section 1 includes one two-man power AND game) 10
a, two selection gates 7.8, and a buffer 9. One input terminal of the AND game 1-10a is connected to the input terminal 20 via the selection gate 8, and the other input terminal is connected to the input terminal 20 via the buffer 9 and the selection gate 7. ing.

The data storage unit 3 is configured similarly to the latch circuit shown in FIG. 8(a), and includes an inverter shown by reference numeral 11 in FIG. NAND gate indicated by 18
a, 17 AND gate indicated by a and symbol 18
The NOR gates a+ 19 a are shown in FIG. 8 (
an inverter designated by 61 in a), 82a;
OR gate 83a, NAND gate 84a, 65a, AND 66a, 87a
The gate corresponds to a NOR gate designated by 88 a + 69 a.

FIG. 2(b) is a timing chart showing the operation of the circuit of this embodiment.

A clock signal CLK whose level is inverted at a predetermined period is input to the clock terminal 21 . This clock signal CL
K is delayed when passing through buffer 4, and is output from buffer 4 as delayed clock signal CLK2.

A clock signal CLK and a delayed clock signal CLK2 are input to the input terminal of the NOR game (NOR game) 5a. Therefore, NO
The R game) 5a outputs a control clock signal CLKI which is normally at L level and becomes H level just before clock signal CLK rises.

The input signal input to the input terminal 20 is input to the AND gate 10a via the selection gate 8 when the control clock signal CLKI is at L level. And the data storage section 3. The output D3 of this AND game) 10a is stored in synchronization with the clock signal CLK.

By the way, in the circuit of this embodiment, the clock signal CL
Immediately before K is inverted from the L level to the H level, the selection gate 7 is on and the selection gate 8 is off. Therefore, the clock signal CLK changes from L level to H level.
Immediately before the level is reversed, the input signal changes from H level to L level.
When the level is inverted, this input signal is delayed by the buffer 9 and input to the AND gate 10a. That is, the output D3 of the AND game 10a changes from the H level to the L level with a delay of the buffer 9 delay time compared to the input signal. Since the timing at which the output D3 of the AND gate 10a is inverted is sufficiently delayed from the timing at which the clock signal CLK rises, the occurrence of spikes is avoided. Therefore, no spike occurs in the output D1 of the OR gate 12a, the output q of the NAND gate 14a, and the output D2 of the AND gate 18a of the data storage section 3, and no spike occurs in the output signal Q either.

FIG. 3(a) is a circuit diagram showing a latch circuit according to a third embodiment in which the present invention is applied to a clocked R-S latch circuit. This latch circuit has two data input control sections 1a
It is composed of a tlbs clock generating section 2 and a data storage section 3.

Since the clock generating section 2 has the same structure as the clock generating section of the latch circuit of the first embodiment, the same parts in FIG. 3(a) as in FIG. 1(a) are given the same reference numerals. A detailed explanation thereof will be omitted.

The data input control section 1a includes one two-man OR gate 4, similar to the data input control section of the latch circuit of the first embodiment.
2, two selection gates 39.degree. 40, and one buffer 141. One input terminal of this OR gate 42 is connected to the reset terminal 24 via the buffer 41 and the selection gate 39, and the other input terminal is connected to the reset terminal 24 via the selection gate 40.
It is connected to the.

Similarly to the data input control section 1a, the data input control section 1b also includes one two-man OR gate 48, two selection games 43 and 44, and one buffer 45. One input terminal of this OR gate 46 is connected to the set terminal 25 via the buffer 45 and the selection gate 43, and the other input terminal is connected to the selection gate 43.
It is connected to the set terminal 25 via 4. and,
The output terminals of the OR gates 42 and 48 are connected to the storage section 3a, respectively.
is connected to the input terminal of the ANDNO gate, 48.

The data storage section 3a is configured similarly to the latch circuit shown in FIG. 5(a). That is, the AND gate designated by numeral 47.48 and the NOR gate designated by numeral 49.50 in FIG. 3(a) are respectively designated by numeral 5 in FIG.
This corresponds to an AND gate indicated by 1.52 and a NOR gate indicated by 53.54.

FIG. 3(b) is a timing chart showing the operation of the circuit of this embodiment.

As explained in the first embodiment, the NAND gate 5 of the clock generating section 2 outputs the control clock signal CLKI, which is normally at the H level and becomes the L level immediately before the clock signal CLK falls from the H level to the L level. is output.

The set signal S input to the set terminal 25 is transmitted to the selection gate 44 when the control clock signal CLKI is at H level.
The signal is input to the OR gate 46 via the OR gate 46. Then, when the output S2 of the OR gate 46 becomes H level, the data storage section 3a synchronizes with the rising edge of the clock signal CLK.
The output signal Q output from the output terminal 22 is set to H level, and the inverted output signal Q output from the inverted output terminal 23 is set to L level.
level.

By the way, in the circuit of this embodiment, the clock signal CL
Immediately before K is inverted from H level to L level, selection gates 39.43 are on, and selection gates 40.43 are on.
44 is in the off state. Therefore, the clock signal CLK
When set signal S is inverted from L level to H level immediately before S is inverted from H level to L level, this set signal S is delayed by buffer 45 and input to OR gate 46 . That is, the output s2 of the OR gate 46 is inverted from the L level to the H level with a delay from the set signal S by the delay time of the buffer 45. Since the timing at which the output S2 of the OR gate 46 is inverted is sufficiently delayed from the falling timing of the clock signal CLK,
No spike occurs at the output S1 of the AND gate 48. Therefore, no spikes occur in the output signal Q and the inverted output signal Q either.

Similarly, even when the reset signal R is input at the falling timing of the clock signal CLK, since the data input control section 1a is provided with the buffer 41, a spike is generated in the output signal Q and the inverted output signal Q. This can be prevented from occurring.

FIG. 4(a) is a circuit diagram showing a latch circuit according to a fourth embodiment of the present invention. This latch circuit is also composed of two data input control sections 1aslbs, a clock generation section 2, and a data storage section 3.

This latch circuit differs from the third embodiment in that the circuit has a negative logic configuration. Therefore, the data input control sections 1a, lb and the clock generation section 2 have a negative logic configuration.

The clock generating section 2 of the latch circuit according to this embodiment has a second
Since the structure is similar to that of the clock generating section of the latch circuit of the embodiment, the same components in FIG. 4(a) as in FIG. 2(a) are given the same reference numerals, and detailed explanation thereof will be omitted.

Further, in the data input control unit ia*tb, the OR gates 42 and 48 in the third embodiment are replaced by the AND gates 42 a +
48a.

Furthermore, the data storage section 3a is configured similarly to the latch circuit shown in FIG. 6(a), and includes OR gates 47a+48a and 49a, 49a in FIG. 4(a).
The NAND gate 50a is connected to the OR gate 51a and 52a and 53 in FIG. 6(a), respectively.
a, corresponds to the NAND gate indicated by 54a.

FIG. 4(b) is a timing chart showing the operation of the circuit of this embodiment.

As explained in the second embodiment, the NOR gate 5a of the clock generating section 2 outputs the control clock signal CLKI, which is normally at the L level and becomes the H level just before the clock signal CLK rises from the L level to the H level. is output.

When the control clock signal CLKI is at L level, the set signal S input to the set terminal 25a is applied to the selection gate 4.
4 to the AND game) 46a. and,
The data storage section 3a has this ANDNO gate 5a output S2.
When the level reaches H level, the output terminal 22
- The output signal Q to be output is set to H level, and the inverted output signal i outputted to the inverted output terminal 23 is set to L level.

By the way, in the circuit of this embodiment, the clock signal CL
Immediately before K is inverted from the L level to the H level, the selection game) 39.43 turns on, and the selection game) 40.4
4 is turned off. Therefore, just before the clock signal CLK is inverted from the L level to the H level, the set signal S
When the signal S is inverted from H level to L level, this set signal S is delayed by the buffer 45 and sent to the ANDNO gate 5.
A is forced. That is, the output S2 of the AND game 48a is delayed from the set signal S by the delay time of the buffer 46,
Inverted from H level to L level.

Since the timing at which the output S2 of the AND game 48a is inverted is sufficiently delayed from the rising edge of the clock signal CLK, no spike occurs in the output S1 of the OR game 48a of the storage section 3a. Therefore, no spikes occur in the output signal Q and the inverted output signal τ.

Similarly, when the reset signal R is input at the timing of the rise of the clock signal CLK, a spike occurs in the output signal Q and the inverted output signal Q because the buffer 41 is provided in the data input control section 1a. can be prevented from happening.

[Effects of the Invention] As explained above, according to the present invention, the data input signal input immediately before the rising or falling edge of the clock signal is
Since the clock signal is delayed until it is completely inverted in the data input control section and then input to the storage section, it is possible to avoid the occurrence of spikes in the output of the latch circuit. Therefore, the latch circuit according to the present invention has the effect of preventing malfunctions of circuits connected at subsequent stages.

[Brief explanation of the drawing]

FIG. 1(a) is a circuit diagram showing a latch circuit according to a first embodiment of the present invention, FIG. 1(b) is a timing chart showing the operation thereof, and FIG. 2(a) is a circuit diagram showing a latch circuit according to a first embodiment of the present invention. A circuit diagram showing the latch circuit according to the second embodiment, FIG. 2(b) is a timing chart showing the operation thereof, and FIG. 3(a)
) is a circuit diagram showing a latch circuit according to a third embodiment of the present invention, FIG. 3(b) is a timing chart diagram similarly showing its operation, and FIG. 4(a) is a circuit diagram showing a latch circuit according to a third embodiment of the present invention. FIG. 4(b) is a circuit diagram showing a latch circuit according to the above, FIG. 4(b) is a timing chart showing its operation, FIG. 5(a) is a circuit diagram showing a conventional R-S latch circuit, and FIG. 5(b) 6(a) is a circuit diagram showing another conventional R-S latch circuit, and FIG. 6(b) is a timing chart showing the same operation.
) is also a timing chart diagram showing the operation, No. 7
Figure (a) is a circuit diagram showing a conventional D latch circuit, and Figure 7 (
FIG. 8(b) is a timing chart showing the same operation, FIG. 8(a) is a circuit diagram showing another conventional D latch circuit, and FIG. 8(b) is a timing chart showing the same operation. L la, ib; data input control unit, 2; clock generation unit, 3; data storage unit, 4,941.45; buffer, 5.14a, 15a+ IEL 19°49a+
50a+ 53a, 54a, 64a+ 65a, 6
B, 69; NAND gate, e, t 1. el; Inverter, 7, 8, 39, 40. 43, 44; Selection gate, 10r 12 al 13 al l 6+1
7+ 42+ 4L 47a+ 48a51a
, 52a+ E32a+ 83a, ee, e'7
;OR gate, 10a, 12y 13+ le
a, 17a+42a. 48a+ 47+ 4L 5L 52+ 6
2+ 63+66 a * 87 a: A N
D gate, 5a, 14+ 15+ 18a,
19a, 4θ, 50, 53.54°6C65, 88a
+89a; NOR gate, 20.79; input terminal,
2L 21a, 72+ 77; clock terminal, 22, 7
4; Output terminal, 23°75; Inverted output terminal, 24+
24a+, 7 L 78; Reset terminal, 25+ 2
5a+ 73.78; Set terminal 7th 'Jttshi l11 72! Clock terminal 73 - t available 6 child 74 - output n terminal for hrj, touch mount 7] Koko

Claims (1)

[Claims] (1) A control clock generator that inputs a clock signal and generates a control clock pulse before the level of the clock signal is inverted; and a control clock generator that inputs a data input signal and generates the data input signal based on the control clock pulse. A latch circuit comprising: a data input control section that delays the time until the level of the clock signal is inverted; and a data storage section that holds the output of the data input control section.