JPS6166571A - Gate pulse controller of thyristor inverter - Google Patents

Abstract

PURPOSE:To accurately control gate pulse without shortening a sampling time by adding a simple hardware to a gate pulse control by a microcomputer. CONSTITUTION:A gate pulse controller by a microcomputer 1 has the first third buffers 2-4 with latches, the first and second timers 6, 7, and a forcibly pattern output circuit 8 having a delay circuit 9 for the prescribed time, and a discriminating flip-flop 10. Thus, a gate pattern signal GP1 and a pattern forcible output signal SP1 are simultaneously written in the buffer 1 and held in the buffers 3, 4 by the microcomputer 1. The output circuit 8 delays an input load signal LP1 to the buffer 3 for the prescribed time when the counted time of the timer 7 becomes longer than the RTC signal output period of the timer 6, and a gate pattern signal GP3 is loaded to the buffer 4 during the period.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a gate pulse control device for a thyristor inverter using a microcomputer.

[Technology since TLT]

Conventionally, a gate pulse control device for a thyrisk inverter using a micro combiator, as shown in FIG.
2 is an interrupt signal 21a of the timer 11 at fixed time intervals.
Sampling control is carried out by , and the gate pattern signal 22a is directly outputted to the gate pulse amplifier 23 by a microprogram.

[Problem that the invention seeks to solve]

However, in method C, in order to perform gate pulse i+IIm with high precision, it is necessary to shorten the sampling time, which shortens the free time of the microcomputer, resulting in the problem that other controls cannot be performed sufficiently. .

[Means for Solving the Problems] In order to solve the above problems, the present invention improves the gate pulse control by a microcomputer by adding simple hardware to increase the sampling time (i+i) without reducing it by 1. Product 1 sentence Nori 1 Tobalus: This enables H control and also prevents the case (11 outputs of Haturn) due to timer malfunction.

〔Example〕

The present invention will be explained below based on the embodiment shown in FIG. In the figure, 1 is a block diagram showing a first embodiment of the present invention, 2 to 4 are first to third latch buffers, 5 is a gate pulse amplifier, 6 and 7 are first and second timers, 8 is a forced pattern output circuit, 9 is a fixed time delay circuit composed of flip-flops, IO is a flip-flop for determining the output condition of the forced pattern, 11 and 12 are OR gates, 13 to 15 are AND gates, 1
6 to 19 are inversion gates.

[Effect]

This operation will be explained below with reference to the time chart shown in FIG.

GP1 and SF3 in FIG. 1 are a gate pattern signal and a pattern forced output signal, respectively, which are simultaneously written into the first latch buffer 2 by the microcomputer 1. The output GP of this first latch buffer 2
2. SP2 is output together with the above write and maintains this state until the next write.

When the input capture signal LPI is input to the terminal G, the second latch buffer 3 inputs the input signal LPI to the terminal G. The signal of SF3 is manually input, this content is output and held until the next LP1 is manually input. The third buffer with lunch 4 also has a terminal G in the same way as above.
A gate pattern signal GP4 is outputted to the gate pulse amplifier 5 by the human input signal LP2.

The sampling interrupt signal RTC is a signal that determines the sampling period of the microcontroller 1, and a pulse is output from the first timer 6 within the period. Since the second timer 7 is manually operated using the interrupt signal RTC as a gate, the count value is reset to the initial value by this signal, and then starts counting down from the set value set by the microcontroller, and then When the 071M output pulse is reached, the 071M output pulse is output.

When the forced pattern output circuit 8 is not operating, during steady state, the counting time of the second timer 7 (from the time when the first timer 6 RT C18 is output until the second timer 7 outputs the GTIM signal) ) is shorter than the RTC signal output cycle of the first timer 6,
If the first timer 6 or the second timer 7 malfunctions due to internal or external factors, the second timer 7
If the count interval is longer than the RT C48 output cycle of the first timer 6, the count value has been reset to the initial value by this RTC, so the GTIM output signal of the second timer 7 will not appear.

As a result, since the manual input signal LP2 of the third latch buffer 4 is not output, the contents of the gate pattern signal GP3 cannot be reflected in the output of the third latch buffer 4, and this is due to the n-combination. Depending on the situation, this may lead to commutation failure of the thyristor/inverter.

The forced pattern output circuit 8 solves the above-mentioned problem, and when the count period 111 of the second timer 7 becomes longer than the RTC signal output period of the first timer 6, the second pattern output circuit 8 The input capture signal Pl to the buffer with latch 3 is delayed for a certain period of time, for example, by two clocks, and during that time, the input capture signal to the third buffer with latch 4 is forcibly generated to capture the gate pattern signal GP3. let

Thereafter, the second latch buffer 3 takes in the gate pattern signal GP2 and latches the output.

The operation signal SP3 to the forced Bakun output circuit 8 sets a "permission signal" when the gate pattern is changed in the sampling period. This is for the purpose of accurately outputting the gate pattern, and manual input signals are used in unnecessary places.
This is to avoid delaying t.

In FIG. 1, the time chart shown in FIG. 3 for the case where the gate pattern data is changed within the sampling period (FIG. 3 shows the counting time of the second timer 7 (GT
This shows a no-kense when the time (time until IM is output) is 4C shorter than the RTC signal output period of the first timer 6.

);, jj! 'j　Explain from + to -.

(7) When the RT C pulse is generated, the output 10a of the flip-flop and PIO is at the "HIGH" level, so the logical product of the AND gate 13 is established and the manual input to the second latch buffer 3 (no. 1. Pl is generated.

The output 5p3 (operation signal to the +ff control pattern output circuit l@8) of the second latch buffer 3 becomes "HIGH" level, and at the same time the flip-flop 10 heliset signal l
Since Ob enters a certain time later than RTC, flip 7
The output 10a of the 0 knob 10 becomes "OW". After the RTC occurs, the second timer 7 finishes counting at a certain time, generates an output pulse G i "l M, becomes the clock power of the flip-flop 10, and makes the output 102 "HIGH".
At the same time, the GTIM signal passes through the OR gate I2, generates a manual input signal LP2 to the third latch buffer 4, and inputs the gate pattern data GP.
3 is input, gate pattern data is output to the gate pulse amplifier 5 and held.

Here, if a malfunction occurs in the first timer 6 and the second timer 7 and the GTIM is not generated before the next RTC signal is generated, the output 10a of the flip-flop 10 is "
LOW'', AND gates 14 and 15 can be logically ANDed, and AND gate 13 cannot be logically ANDed.

Therefore, when the next RTC signal is generated, the logical product by the AND gate 15 is established, so the RTC signal generates the human power capture signal LP2, and causes the third latch buffer 4 to capture the human power and launch it.

After that, the output 9a is generated from the delay circuit 9 by mistake for a certain period of time, so the AND of 14 is established, the human power input signal is generated, Pl is generated, and the second latch buffer 3 is configured to input the human power. .

The flip-flop 10 is initialized by the output SP3 of the second latch buffer 3.

〔Effect of the invention〕

As described above, according to the present invention, by adding open-type hardware to gate pulse control by a microcomputer, it is possible to shorten the sampling time (without shortening the sampling time) and enable highly accurate gate pulses: t, II tall. In addition, it is possible to prevent erroneous output of gate patterns due to malfunction of the timer, and furthermore, it is possible to easily control the gate pulses of the multi-thyristor inverter.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are time charts showing its operation, and FIG. 4 is a block diagram showing the configuration of a conventional control device. 1: Microcomputer 2: First latch buffer 3: Second latch buffer 4: Third latch buffer 5: Gate pulse amplifier 6: First timer 7: Second timer 8: Force Pattern output circuit 9, delay circuit 1O; Furinov Fronov. 11.12 Nior gates 13 to 15: AND gates 16 to 19: Inversion gates GPI-Gl)3 Gate pattern signal SP1. S.P.I.
Pattern strong; -1 output signal SP3: Operation signal Ll to forced pattern output circuit)1. LP1 manual input signal RTC: Numbering interrupt No. 13 GTIM: Pattern output time No. 1z CLK: Oscillation frequency Fig. 1 Fig. 2 Fig. 3 (a) CLK . (j) GP3 4 B Figure 4

Claims (1)

[Claims] 1. In a gate pulse control device for a thyristor inverter that performs gate control by a microcomputer, a first buffer receives and holds Nth gate pattern data from the microcomputer within the N-1st sampling time; Within the N-1st sampling time, a count value corresponding to the Nth gate pattern data output timing is set by the microprocessor,
a first timer that starts counting from the start time of the Nth sampling and generates a pulse when the count setting value is reached; a second timer that generates an interrupt pulse that determines the processing cycle of the microcomputer; a second buffer that inputs and holds the gate pattern data of the first buffer input within the N-th sampling time at the beginning of the N-th sampling time; A third buffer inputs the gate pattern data of the second buffer according to the output pulse of the first timer, holds it and outputs it, and when the gate pattern data is updated within the Nth sampling time. , when the gate pattern data of the second buffer is not updated due to a counting malfunction of at least one of the first or second timer, the gate pattern data of the second buffer is forced to be input to the third buffer, and the gate pattern data is held and output. A gate pulse control device for a thyristor inverter, characterized by comprising a pattern output circuit.