JP3090696B2 - FSK demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FSK modulation type demodulation circuit used in wireless / wired communication.

[0002]

2. Description of the Related Art In a conventional FSK signal demodulation circuit, FIG.
, The periods λ ₁ , λ of the FSK frequencies f ₁ , f _2
2 is provided with an FSK frequency determination timer that is set to a time t _{s such} that λ ₂ <t _s <λ _1, and the next until the set time t _s elapses from the leading edge (or the trailing edge) of the FSK signal. If the leading edge (or trailing edge) is detected, the FS of the frequency f ₂
It determined that K signal, the next leading edge until the lapse of set time t _s was to determine the FSK signal of frequency f ₁ is not detected. In this circuit, for example, as shown in FIG.
When receiving the SK signal, the time that can recognize the change of the FSK frequencies, if the FSK frequency changes from f ₂ to f ₁ is the time that has elapsed t _s time from the start of the leading edge of f _1, from f ₁ If changes to f ₂ is the second leading edge of the first leading edge time when the lambda ₂ has elapsed since the detected time i.e. f ₂ of f _2.

[0003]

In [0005] the demodulation circuit described above, the output time of the demodulation signal FSK frequency with respect to time T ₁ is f ₁ is shortened by (t _s -λ _2), and conversely, the FSK frequency output time of the demodulated signal with respect to time T ₂ is f ₂ becomes longer by (t _s -λ _2). Therefore, waveform distortion occurs in the demodulated signal.

[0004]

The FSK demodulation circuit of the present invention solves the above problem by the following means. In the FSK signal demodulation circuit, either the leading edge or the trailing edge of the FSK signal is used. a detection unit which outputs one of the differential signals, are set in advance period lambda ₁ of the FSK signal, ₂ lambda respect λ ₂ <t _s <λ ₁ becomes time t _s, the differential signal output from the detecting unit A frequency determination timer unit to be started, a demodulation unit that demodulates to a signal of digital value “0” or “1” by comparing a set time of the timer with a time interval of a differential signal output from the detection unit, The change point of the demodulated signal output from the demodulation unit is defined as (t _s −λ ₂ ) when the FSK signal changes from f ₁ to f ₂ .
Or from f ₂ delayed by at the time of changes to f ₁ (t _s
-[Lambda] ₂ ).

[0005]

According to the FSK demodulation circuit of the present invention, first, the detection circuit
Outputting either one of the differential signal of the leading or trailing edge of the SK signal, and a frequency determination timer set to a time t _s by the generation of the differential signal is started. The demodulation circuit performs demodulation by comparing the output time from the frequency determination timer with the generation time interval of the differential signal output from the detection circuit. The demodulation signal includes the above-described waveform distortion. In other words, the demodulated signal FSK frequency with respect to time T ₁ is f ₁ is (t _s -λ ₂₎ only becomes short, the demodulated signal FSK frequency with respect to time T ₂ is f ₂ is reversed (t _s -λ ₂₎ Is only getting longer. But,
In the waveform distortion compensation circuit, to the demodulated signal including the waveform distortion, the change point of the signal delay or upon change from f ₁ to f ₂ by (t _s -λ _2), or from f ₂ to f ₁ of correcting the waveform distortion by advancing only (t _s -λ ₂₎ during the change, and outputs a free demodulated signal waveform distortion.

[0006]

DETAILED DESCRIPTION FIG. 1 is a circuit diagram showing an embodiment of an FSK demodulation circuit of the present invention, to detect the leading edge of the FSK signal detection circuit, f ₂ from f ₁ of the FSK frequency waveform distortion compensation circuit
The transition point of the demodulated signal corresponding to the transition point to (t _s −
This is an example of delaying by λ ₂ ). FIG. 2 is a timing chart of the circuit shown in FIG.

In this embodiment, as shown in FIG. 2A, the FSK signal a is a pulse signal having two frequencies f ₁ and f ₂ , and the time at which the frequency f ₁ is T ₁ and f ₂ . a certain time is assumed to be T _2. Incidentally, FSK frequency <br/> number f ₁ of the present embodiment is 1/8, f ₂ of the frequency of the clock signal b is 1/4 of the frequency of the clock signal b.

[0008] The leading edge detection unit 1 uses the FS shown in FIG.
A differential signal synchronized with the leading edge of the K signal a is output. First F
When the SK signal a is input to the data input terminal of the flip-flop 11, it is captured at the timing of the rising edge of the clock signal b (see FIG. 2B). Next, when the pulse signal c is input, the flip-flop 12 outputs a pulse signal d that is delayed by one cycle of the clock signal b from this signal. The pulse signals c and d are input to the AND gate 13, and a pulse signal e having a pulse width of one cycle of the clock signal b is output. This is a differential signal obtained by detecting the leading edge of the FSK signal, and the period of the pulse signal e matches the periods λ ₁ and λ ₂ of the FSK signal.

The frequency determination timer 2 has a function of F
A time t _s satisfying λ ₂ <t _s <λ ₁ (in this embodiment, a time corresponding to six periods of the clock signal b) is set for the periods λ ₁ and λ _{2 of the} SK signal, and the generation of the differential signal is performed. Reset and start. Unless the next differentiated signal is input before the set time t _s elapses after the timer starts, the output signal f becomes L level. If the next differential signal is input before the set time t _s elapses, the timer is reset and restarted. At this time, the output signal f
Remain at the H level.

The demodulation section 3 outputs a demodulation signal g shown in FIG. 2 (g) to the output signal e of the leading edge detection section 1 based on the output signal f from the frequency determination timer 2. That is, H is output if the next pulse signal is input before the timer time t _s elapses after the generation of the pulse signal e, and L is output if the next pulse signal is not input even after the timer time t _s elapses. I do. However, as shown in FIG. 2G, the demodulated signal g includes waveform distortion. That is, the time when the demodulated signal g is L is the time T when the frequency of the FSK signal is f _1.
It is shorter by (t _s -λ ₂₎ to _1, and conversely, to time T ₂ frequency is f ₂ times the demodulated signal g is H FSK signal (t _s -λ ₂₎ Is only getting longer. In this embodiment, the time (t _s 1-? ₂₎ is the length of two cycles of the clock signal b.

The demodulated signal g is input to the waveform distortion compensator 4 to correct the waveform distortion. Since the demodulated signal g is input to the data input terminal of the flip-flop 41 and to the reset terminals of the flip-flops 41 and 42, the output signal of the flip-flop 42 is
If the demodulated signal is L, it always becomes L, and when it changes from L to H, it changes to H with a delay of two cycles of the clock b. Therefore, the output signal h is longer than the demodulated signal g by 2 clocks for L, and shorter by 2 clocks for H. In this way, the waveform distortion (t _s −λ ₂ ) included in the demodulated signal g is compensated.

[0012]

As described above, the FSK modulation signal demodulation circuit of the present invention can accurately demodulate an FSK signal including two frequencies.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an FSK demodulation circuit of the present invention.

FIG. 2 is a timing chart of the FSK demodulation circuit shown in FIG. 1;

FIG. 3 is a diagram illustrating a relationship between a cycle of two frequencies of an FSK signal and a set time of a frequency determination timer.

FIG. 4 is a diagram for explaining that a conventional circuit causes waveform distortion in a demodulated signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Leading edge detection part 2 Frequency judgment timer 3 Demodulation part 4 Waveform distortion compensation part 11 Flip-flop 12 Flip-flop 13 AND gate 41 Flip-flop 42 Flip-flop

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-184356 (JP, A) JP-A-63-26144 (JP, A) Jikai Sho 60-82859 (JP, U) (58) Field (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (1)

(57) [Claims] 1. A digital value "0" and "1" the first frequency f ₁ and the second frequency f ₂ of the signal (where, f ₁ <f ₂
And their periods are λ ₁ and λ ₂ . ) And corresponding F
In the demodulation circuit in SK signal, a detection unit which outputs either one of the differential signal of the leading or trailing edge of the FSK signal, the period lambda ₁ in advance FSK signal, with respect to lambda ₂ lambda
₂ <t _s <λ _1, which is set to the time t _s, and which is started by the differentiated signal output from the detector, a frequency determination timer, and the set time of the timer and the time of the differentiated signal output from the detector A demodulation unit that demodulates to a signal of digital value “0” or “1” by comparing intervals,
The changing point of the demodulated signal output from the demodulating section from f ₁ of the FSK signal upon change to f ₂ (t _s -λ ₂₎ or from f ₂ delaying the time changes to f ₁ (t _s 1-? ₂ )
A FSK demodulation circuit, comprising: