JPH0342762Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to a demodulator for use in optical communications, and more particularly to a demodulator for Manchester code signals replaced with unipolar levels. FIG. 1 is a waveform diagram of a unipolar level signal representing a Manchester code. As shown in the figure, in this Manchester code signal, one bit consists of a first half and a second half, and when one part is at O level, the other part is always at +V level. Each bit is determined to be "0" or "1" depending on which part is at the +V level. When a Manchester code signal propagated through an optical transmission line as a single-wavelength optical signal is converted into an electrical signal by an O/E converter (a device that converts an optical signal into an electrical signal), it usually becomes an electrical signal as shown in this figure. becomes a unipolar level signal. In the following, the unipolar level Manchester code signal generated through the O/E converter after propagating through the optical transmission line will be simply referred to as an Rx signal (received signal). The duty ratio within one bit of this Rx signal is
Bandwidth and threshold level of O/E converter,
Furthermore, it changes depending on the characteristics of the E/O converter (device that converts an electrical signal into an optical signal) on the transmitting side. When the duty ratio fluctuates in this way, the timing of the clock in the Rx signal shifts. Also, Rx
If the noise component of the signal is large, the waveform of the Rx signal will be disturbed. FIGS. 2a, b, and c are waveform diagrams of the Rx signal, and the points indicated by arrows are clock timings. Figure a shows the case where there is no waveform disturbance due to fluctuations in the duty ratio or noise, Figure b shows the case where the clock timing is shifted due to fluctuations in the duty ratio, and Figure c shows the case where the waveform is greatly disturbed by noise. Each is shown below. Conventional demodulators for Manchester code signals generate and demodulate clocks by detecting the rising and falling edges of the pulses of the Rx signal. If the waveform is disturbed as in
It was easy to misidentify the time point indicated by the arrow as the clock timing and cause a code error in the demodulated signal. An object of the present invention is to provide a demodulator for a Manchester code signal that is less likely to cause code errors in the demodulated signal even when the Rx signal has a duty ratio fluctuation or a large noise component. The demodulator of the present invention demodulates a Manchester code signal in which the first bit is a predetermined pulse; 2n times the transmission rate of each bit of the Manchester code signal (n is the number of corners of 4 or more) means for receiving a logic "1" bit signal as the clock signal and the predetermined pulse to generate a bit selection signal indicating the first half and the second half of the Manchester code signal; means for sampling each bit to detect a signal pattern of a series of n "1"s and "0"s;
When the number of "1"s in the bit selection signal and the signal pattern exceeds n/2, each bit is set to "1" regardless of the first half and the second half indicated by the bit selection signal. It is determined that the bit selection signal indicates the second half when each of the consecutive n/2 of the signal patterns is "1" and "0" in order, and the bit selection signal indicates the second half of the signal pattern. When each of the n/2 consecutive bits is "0" and "1" in turn, it is determined by comparing the bit selection signal with a pattern in which each bit is determined to be "1" when the bit selection signal indicates the first half. and means for determining whether each bit is "1" or "0". Next, to describe the operation of the present invention, when demodulating a Manchester code signal (Rx signal) from the transmitting side, the demodulator of the present invention completely eliminates errors that occur in the demodulated signal due to duty fluctuations and the influence of noise. No compensation structure has been adopted. The reason for this is to avoid complicating the circuit configuration, and is based on the idea that compensation within a certain detection limit is sufficient for the system. In other words, in detail, in this demodulator,
As is clear from Table 1 and Figure 6, when the signal pattern is n = 4 (1Q to 4Q), the following a,
There are basic detection limits for b and c. (a) Correct demodulation cannot be performed when the duty fluctuation exceeds 75% of the one-pulse signal width (first half + second half). (b) When duty variation is 75% of one pulse signal width, noise influence (1 or more) in the area exceeding 75%
When this occurs, the corresponding first half/second half cannot be demodulated correctly. (c) Even if the duty fluctuation is less than 75% of the 1-pulse signal width, the
That is, when two or more noises affect the first half of a logic "1" bit signal and the second half of a logic "0" bit signal, the corresponding sections may not be demodulated correctly. In this demodulator, the basic detection limits a to c described above are
Based on patterns A to G shown in Table 1 with
Determine whether each bit of the Rx signal is “1” or “0”.
In particular, when the bit is in an ambiguous area (gray zone) that does not correspond to patterns A to E, it can be determined based on patterns F and G (1Q to 4Q, BSEL). This demodulator demodulates the Rx signal as described above, but the reliability of the demodulated signal due to the influence of duty fluctuations and noise can be improved in proportion to the number of n signal patterns, and the gray zone By making a determination based on the bit selection signal (BSEL) and n signal patterns (1Q to 4Q), it is possible to correctly demodulate the bits within the detection limit. Therefore, errors are less likely to occur in the demodulated signal. Next, the present invention will be explained in detail with reference to the drawings. Figure 3 is a block diagram of an embodiment of the present invention;
This figure is a circuit diagram of the signal pattern comparison circuit of FIG. 3, and FIG. 5 is a waveform diagram showing an example of an Rx signal input to this embodiment. The Rx signal received by this embodiment is
"1" is always transmitted in the first bit, and the maximum number of bits is 640 bits. In this embodiment, determination is made for each 1/2 width of 1 bit of the Rx signal 101, that is, the first half and the second half of 1 bit, the results are demodulated into an NRZ signal, and the NRZ signal is output. do. In FIG. 3, the four-stage shift register 1
samples the Rx signal 101 using a clock having a frequency eight times the transmission rate of the Rx signal 101 (hereinafter referred to as 8MCLK), and sends the sampling output to the signal pattern comparison circuit 3. The synchronous circuit 2 receives the first bit "1" of the Rx signal from 8MCLK and the output 1Q of the 4-stage shift register 1, detects the rising edge of the pulse, and separates the first half and second half of each bit of the Rx signal. A bit selection signal (hereinafter referred to as BSEL) is generated. In addition, a clock with a frequency twice the transmission rate (hereinafter referred to as
2MCLK) and a clock (hereinafter referred to as MCLK) with the same frequency as the transmission rate. Note that 8MCLK is generated by another oscillator (not shown) that is asynchronous with the Rx signal. The signal pattern comparison circuit 3 receives the sampling output from the four-stage shift register 1 and the output from the synchronization circuit.
It receives BSEL and 2MCLK, and compares the sampling output and BSEL with a preset signal pattern at a cycle of 2MCLK, thereby determining whether it is "1" or "0" and outputting it. Also,
The signal pattern comparison circuit 3 is composed of an AND circuit as shown in Fig. 4, and outputs by operating the flip-flop circuit provided on the output side at 2MCLK, so that the duty ratio of each bit is 50%.
An Rx data signal 110 is obtained. The D-type flip-flop circuit 4 samples the Rx data signal 110 with MCLK from the synchronous circuit 2,
A unipolar NRZ signal 111 is output. Also,
When the synchronization circuit 2 detects the end of the Rx signal based on the RX data signal 110, it enters a state of waiting for the next Rx signal.

【table】

[Table] Table 1 is a table showing signal patterns stored in advance by the signal pattern comparison circuit 3. 1st stage output 1Q of 4 stage shift register 1, 2nd stage output 2
Q, 3rd stage output 3Q, 4th stage output 4Q and
When the BSEL combination corresponds to any of the signal patterns A to G in Table 1, the signal pattern comparison circuit 3 determines that 1/2 bit is "1". Note that "-" in the BSEL column of Table 1 indicates that BSEL may be either "0" or "1".
Also, BSEL "1" means the first half of each bit,
"0" indicates the latter half. FIG. 6 is a timing chart showing an example of each part signal of this embodiment, and shows the case of an Rx signal whose duty ratio deviates from 50%. Normally, the pulse width of each bit of the Rx signal is four cycles of 8MCLK, but in this case it is longer, six cycles, and since 8MCLK is asynchronous with the Rx signal, it may deviate from the rising position of the pulse. ing. Sampling output 1Q, 2Q, 3 from 4-stage shift register 1
Q, 4Q, and BSEL from the synchronization circuit 2 are compared and determined in a signal pattern comparison circuit 3 at a cycle of 2MCLK to generate an Rx data signal.
At clock 1 of 2MCLK, 1Q to 4Q and BSEL are each "1", so they are determined to be "1". Similarly, at clock 2, 1Q and 2Q are "0" and 3Q and 4Q are "1", but since BSEL is "0", they are "0".
It is determined that The Rx data signal becomes an NRZ signal by being sampled with MCLK. In this way, even if the waveform of the Rx signal is disturbed due to noise etc., as in the case where the duty ratio shifts,
Demodulation with fewer errors can be performed. As explained above, according to the present invention, O/E
It is possible to correctly demodulate changes in the Rx signal due to fluctuations in the duty ratio generated in the converter and waveform disturbances due to noise, etc., and it is possible to reduce the error occurrence rate of the demodulated signal.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram of the Manchester code signal replaced with a unipolar level, Figure 2 a, b, and c are
RX signal waveform diagram, Figure 3 is a block diagram of one embodiment of the present invention, Figure 4 is a circuit diagram of the signal pattern comparison circuit of Figure 3, and Figure 5 is input to the embodiment of Figure 3. A waveform diagram showing an example of the Rx signal, and FIG. 6 are timing diagrams of various signals in this embodiment.

Claims (1)

[Claims for Utility Model Registration] In a demodulator that demodulates a Manchester code signal in which the first bit is a predetermined pulse; ) and a logic "1" bit signal as the predetermined pulse to generate a bit selection signal indicating the first half and the second half of the Manchester code signal; means for sampling each bit of n to detect a signal pattern of a series of n "1"s and "0"; When the bit selection signal exceeds the bit selection signal, each bit is determined to be "1" regardless of the first half and the second half indicated by the bit selection signal, and each of the consecutive n/2 bits of the signal pattern is sequentially set to "1". ” and “0” when the bit selection signal indicates the second half, and when each of consecutive n/2 of the signal pattern is “0” and “1” in turn, the bit selection signal means for determining whether each of the bits is "1" or "0" by comparing with a pattern in which each of the bits is determined to be "1" when the bit selection signal indicates the first half; A demodulator characterized by: