JPS5799851A - Signal transmission system - Google Patents
Signal transmission systemInfo
- Publication number
- JPS5799851A JPS5799851A JP55176230A JP17623080A JPS5799851A JP S5799851 A JPS5799851 A JP S5799851A JP 55176230 A JP55176230 A JP 55176230A JP 17623080 A JP17623080 A JP 17623080A JP S5799851 A JPS5799851 A JP S5799851A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- input signal
- outputs
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4902—Pulse width modulation; Pulse position modulation
Landscapes
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To perform signal transmission of high quality free of variation in pulse width, by discriminating the voltage level of an input signal a prescribed time after the input signal is detected, and by sending a modulated and encoded signal after the processing of FFs, a delay circuit, etc. CONSTITUTION:A pulse-width discriminating circuit 1 discriminates whether an input signal has logic 0 or 1 at a prescribed time after the input signal rises, and sets an FF2-0 when it has logic 0, or an FF2-1 when the logic is 1. The outputs Q of the FF2-0 and FF2-1 are inputted to a delay circuit 4 through an OR circuit 8, namely, its inverted signal is supplied to the clear terminal of the circuit 4. A signal C delayed by a prescribed time at the circuit 4 and the outputs Q' of the FFs 2-0 and 2-1 are inputted to EORs 5-0 and 5-1, whose output signals E and F are inputted to terminals J and K of a J-KFF6. The FF6 outputs an encoded signal G which corresponds to the logical value of the input signal. A demodulator outputs a demodulated signal through the processing of a synchronizing circuit, a delay circuit, an AND circuit, and a pulse-width generating circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55176230A JPS5799851A (en) | 1980-12-13 | 1980-12-13 | Signal transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55176230A JPS5799851A (en) | 1980-12-13 | 1980-12-13 | Signal transmission system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5799851A true JPS5799851A (en) | 1982-06-21 |
| JPH0311140B2 JPH0311140B2 (en) | 1991-02-15 |
Family
ID=16009903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55176230A Granted JPS5799851A (en) | 1980-12-13 | 1980-12-13 | Signal transmission system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5799851A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59195855U (en) * | 1983-06-10 | 1984-12-26 | 日本電気株式会社 | demodulator |
| JPS60501533A (en) * | 1983-06-08 | 1985-09-12 | アメリカン テレフオン アンド テレグラフ カムパニ− | Multifunctional data signal processing method and device |
-
1980
- 1980-12-13 JP JP55176230A patent/JPS5799851A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60501533A (en) * | 1983-06-08 | 1985-09-12 | アメリカン テレフオン アンド テレグラフ カムパニ− | Multifunctional data signal processing method and device |
| JPS59195855U (en) * | 1983-06-10 | 1984-12-26 | 日本電気株式会社 | demodulator |
| JPH0342762Y2 (en) * | 1983-06-10 | 1991-09-06 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0311140B2 (en) | 1991-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ES8206935A1 (en) | Signal wave control circuit | |
| JPS56109023A (en) | Channel selection system | |
| JPS5799851A (en) | Signal transmission system | |
| JPS5647139A (en) | Optical transmitting signal-break detecting circuit | |
| JPS56120246A (en) | Waveform shaping circuit | |
| JPS6460036A (en) | Frame signal transmitting system | |
| JPS5643854A (en) | Control system of received carrier detecting circuit | |
| JPS56111331A (en) | Two-dimentionally applied type automatic equalizer | |
| JPS56117423A (en) | Binary coding circuit by multistage threshold level | |
| JPS5792413A (en) | Demodulation system for phase-modulated signal | |
| JPS57152725A (en) | Discriminating circuit for signal pulse width | |
| JPS57182834A (en) | State change detecting circuit | |
| JPS5333011A (en) | Information processing console unit | |
| JPS564957A (en) | Bus circuit | |
| JPS56131242A (en) | Signal receiving circuit | |
| JPS6430321A (en) | Flip flop circuit | |
| JPS56164622A (en) | Signal discriminating circuit | |
| JPS56100581A (en) | Displaying device for sound multiplex receiving mode | |
| JPS5784643A (en) | Signal separation circuit | |
| JPS56119561A (en) | Discriminating and reproducing circuit | |
| JPS56108968A (en) | Measuring method for center frequency of narrow band irregular signal | |
| JPS5276808A (en) | Discrimination of digital multilevel transmission | |
| JPS5762790A (en) | Motor drive control device | |
| JPS53106108A (en) | Signal transmitting circuit | |
| JPS55147821A (en) | Digital filter |