JPS60501533A - Multifunctional data signal processing method and device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Method and apparatus for multifunctional data signal processing Background of the invention The present invention relates to a method and apparatus for data signal processing, particularly to signal bit code conversion and METHODS AND APPARATUS USEFUL FOR FUNCTIONS SUCH AS PRE-EQUALIZATION.

As is known to those skilled in the art, the design using different combinations of binary 1 and O signal bits is The process involves converting one digital signal code to another code representing the same information.

As an example, N.M. Eng. U.S. Pat. No. 3,0], 1.1.65 by A. be.

However, in these systems, the individual bit signals are the same in both codes. It is usually expressed in the same way. That is, a binary 1 bit is The binary O is represented in the same way in both codes.

Binary signal bits are encoded differently in both baseband and modulation formats. can be expressed. For example, in baseband, there is a pulse A bipolar non-zero J-Z (NRZ) format. Similarly, the modulation method Luta pit signals can also be frequency or phase shifted, amplitude modulated, or frequency modulated. It can be expressed as Regardless of the bit representation format, each bit representation format, this This is often called bit representation code or bit representation modulation. There may be times when it is necessary to Sex/English - Quesnel Jr. (HAQue snell.

No. 4,100,54.1 to Jrl, a binary signal of the type NRZ The signal bits are converted to Manchester format by a multiplexing technique. D.E. U.S. Pat. No. 3,774,1.78 to DE-Curtis Now we have a 2-bit shift register and a contingency theory with a clock equal to the bit rate. Using a logic circuit, the NRZ code is calculated between the bit between 1 and the adjacent zero bit. Converted to pre-art code with transitions.

Mi croelectron -Re 1jab magazine, volume 22, page 4, 759- 767. 1982 Nis.M.Positsuk (S.

The paper “Digital formation of modulated waveform data J ('XDig ital Generation of Data Modulated Wav eforms") sets the clock to each input data hit faster than the data. speed and select one or the other of the two forms of the same input data bit state. It is applied to a tart traversal filter to generate a modulated output.

fLt, human code conversion for wireless transmission often has undesirable effects. arise. Be11.5ysternTechnical Journal1 magazine 1 January 979 issue, pages 123=143, R, EFi [Advanced Automobile Telephone Service Equipment Testing Subscriber Set] To J (1l Aclvanced Mobile Phone 5 service A 5ubscriber Set for the Equipment Te In the Manchester bit encoder in Figure 1O of 5t"], the Bessel low-pass filter is is used, followed by an exclusive OR operation and an integration. This filter is Bandlimits the signal while preserving the phase relationship between the different components of the signal and It reduces the amplitude of frequency components outside the line frequency channel. but, Such a filter has an output amplitude that depends on the data pattern. This output amplitude The slam dependence in the system affects the system error rate, and the error rate also depends on the pattern. In the present invention, multiple data signals input information about the state are dependent on each other. are collected and the characteristics of the output signal waveform are determined. The state is the state of the input data signal. For use with local clock signals that have a speed greater than twice the speed of the highest frequency component. 4. Configure the desired output signal wave. The combinational logic circuit is controlled to achieve the desired result.

Brief description of the drawing Various features, objects, and advantages of the invention will be apparent from the detailed description that follows and the description that follows. It will be better understood with reference to the accompanying drawings.

Figure 1 shows a case where the signal processing circuit of the present invention is applied to a data signal bit format conversion device. Figure 2 shows the circuit diagram of the above-mentioned Bessel filter type technology. To demonstrate the improvement achieved by the invention, the output signal spectrum of the processing circuit is It is a diagram showing the size, Figures 3 to 6 are signal waveforms used to achieve the signal processing in Figure 1. This is a diagram.

detailed description The signal processing circuit shown in Figure 1 handles an NRZ input signal that is unbalanced with respect to the ground level. is configured to convert the Manchester output data signal to a balanced signal with respect to the ground level. has been completed. In the Manchester, or split-phase coding system, the binary state is encoded by transitions rather than amplitude or phase. Bitcoin is usually is represented by a negative going transition, and hit O is represented by a positive going transition. this The DC component is removed by Such signals can be transmitted, for example, by a radio transmitter (not shown). Modulate the output signal of 5*1q6o-5o15aa (3) It can be applied to The intermediate signal processing performed between the input and output in Figure 1 is - As an example, we use bitcode conversion, which is based on the input data signal state and locally By addressing the read-only memory 10 using the generated clock signal. The combinatorial table lookup function is used. This read-only memory stores the waveform Acts as a generator. The local clock signal is generated by counting the output of the oscillator 11. It is made. The oscillator output is passed through buffer 12 to three 4-bit binary counters. is applied to a counter group 13 consisting of counters 16, 17 and 18. Output of oscillator 11 The force frequency is much higher than twice the NRZ input kadeka datat speed, and It is the product of the integer power of and the data frequency. In this example, the speed is 10 kilobits per second. The oscillator output is 10.2 for the signal processing circuit that receives the NRZ input Cadeca data. It is 4 MHz.

The oscillator output passed through the buffer is divided into three 4-bits of counter group 13, viz. It is applied in parallel to the clock input of the 1/16 down power counter stage. These are the notations in the diagram. As shown in the above, this is a rising trigger input. 1st stage] The two control inputs of 6 are Both are connected to the positive bias of the positive power supply 19 through the resistor 20 and are permanently energized. There is. The overflow output RC of stage j6 is applied to the energizing force of both stages 170. Therefore, the latter stage is energized only when the first stage 16 overflows. similar In addition, the overflow outputs of stages 16 and 17 are connected to the respective attachments of the 30th counter stage 18. force is applied to the force input. Therefore, the latter stage has the first two stages 16 and 17 turned on at the same time. energized only when the bar flows.

All three counter stage clear inputs are connected to voltage source 2, shown with a circled plus sign. 1 positive bias and permanently deenergized. The symbol of this voltage source is , connected to the positive terminal of a power supply that also has a reverse polarity terminal connected to ground. It means to do something. Other voltage sources are similarly indicated with circled polarity symbols in the diagram. Ru. Similarly, the parallel input energization terminal connects the positive bias of power supply 22 to the inverting input terminal. 6-1.8, permanently deenergized by applying It is.

], the lowest two bits of the counter stage 16, and the most significant two bits of the counter stage 18. The outputs from all stages of counter group 13 except for The two brigadier signals are connected in parallel bits. These counting phase signals are It is applied to the NRZ input Cadeca data signal input during the signal hit time, but the method is explained below. The details will be explained later.

A 2-bit shift register including D-type flip-flop circuits 23 and 26 has an input It is provided to collect information regarding the signal state of NRZ data.

This register receives, for example, 10 kHz from the second bit of the third counter stage 18. z bit rate clock signal. NRZ input signal is flipped is applied to the D input of the flip-flop 23, and the Q output of this flip-flop is applied to the second flip-flop. It is applied directly to the D input of the flip-flop 26. During this period, the Q output will fluctuate. Along with the Q output of the flop 26, among the address information of the read-only memory 10, It is applied as two bits. These two address bits are Address number 11 is a07i1 to al.

These are bits a7 and a8.

In bit code conversion from NRZ to Manchester, each Manchester bit The shape of the waveform is determined by the current bit state of the input NRZ data bits and the same NRZ input signal. It is mainly determined by the human status immediately before the issue. Therefore, for 2 bits There are four possible distinct bit state combinations, which are the Manchester output Determine the main shape. Therefore, a 2-bit circuit consisting of flip-flops 23 and 26 The parallel output of the shift register indicates the current and previous hit state of the input signal. and is used to address ROM10. More generally, 8 If n input bit states are used to define the shape of the output signal bit, then 2 n bit state combinations are possible. At this time, ROMI O is a combination of these 2n different output bit waveforms representing .

Each of the stored waveforms, in this example, has 128 different time phases. is represented in memory as a sampled value. These values are It can be selected by the upper 7 bits (maximum 10kHz bits) of the counter group output. , these are applied to the lower 7 bits aO to a6 of the address input of ROM10. There is. Another 2-bit address of ROMI O, a9 and alo, is 11 addresses. These are the two most significant bits of the address input. These two bits use another signal processing method. In order to perform are doing. Another type of signal processing here refers to testing and providing a wide range of characteristics to the transmission system. For example, it refers to something that performs data signal conversion in different amplitude ranges. these In the processing circuit shown in the figure, the 2-bit input of (not shown).

Each of the sampling values stored in ROMI O is an 8-pit binary encoded number, Its value is determined by the method described below. These binary encoded samples The switching value appears on output leads QO to Q7 of ROM10 and is output to data latch register 2. 7 is applied to the corresponding input. The latch register is 8 D-type flip-flops. Consists of. As is clear from the above explanation, the effective waveform output from ROMI O The sampling rate is much greater than twice that of the NRZ human-powered tray.

In this embodiment, the sampling rate of the ROM output is 1.280 MHz.

This high sampling rate allows data bit rates and higher enables spectrum control in For example, ideally 64 Although it is a high part by 0kHz, considering the quantization noise.

It is 80kHz from the carrier wave. The third output bit of the tenth counter stage 16 is The clock resistor 270 is applied as a clock to energize the power. this latch The frequency of the clock is 1.28 MH2 in this embodiment.

The output of latch register 27 is continuously energized. Because this Regis The clear input of the controller is connected to the positive bias from voltage source 28 through resistor 29. This is for the purpose of These latched outputs are connected to a 300Å digital to analog converter. Directly connected The operating potential is derived from the ground connection. In addition, the converter has the following functions: A reference current is supplied from a positive voltage source 33 via a resistor 35, and its return path is a resistor. 36 is connected to ground. The output of ROMI0 is determined by that clock. ROM The clock pulse is applied to the latch 27 at twice the maximum frequency of the IO address input. By inputting, the input to the latch is made only after the ROM output has stabilized, The input to converter 30 is also stable.

The output from converter 30 is provided as a current output on lead 37 and is applied to operational amplifier 38. Applied to the inverting input terminal. One of the functions of this amplifier is to convert the current value into a voltage Provided for converting to a value. Therefore, its non-inverting input terminal is connected to ground. The inverting input terminal is applied to the positive voltage source 33 via the resistor 39. difference Furthermore, a parallel combination of resistors and capacitors consisting of a resistor 40 and a capacitor 41 is used for amplification. This is a feedback path from the output of the converter to the sono-inverting input terminal, and is a single-pole low-frequency Acts as a filter and quantizes at a sampling rate of 1.28 MHz It smoothes out the noise. If the new station frequency is higher than twice the data rate, e.g. 80kHz was found to be a good value. Depending on this filter, 1(l No large phase shift occurs in the kHz NRZ signal band.

The output of amplifier 38 is connected to the non-inverting input of operational amplifier 43 via variable voltage divider 42. Applied to the terminal. This amplifier is a unity gain amplifier and is connected via a resistor 46 to a separate The operational amplifier 470 forms a low impedance output for the inverting input.

Amplifier 47 has a negative feedback connection by resistor 48, which connects the amplifier's original The level is set by this. Furthermore, from the inverted output via the resistor 49, with another negative feedback connection to the non-inverting input of the amplifier. The non-inverting input is and is connected to ground via a resistor 50. This configuration makes the amplifier balanced The output operation is performed, and the output of the code converter is converted into a balanced force via resistors 51 and 52. Supplied as a signal.

Figure 2 shows the improvements realized in the circuit of Figure 1 using the ROM conversion method as described above. This is shown in comparison with a Bessel filter type. The diagram shows the frequency spectrum It shows the relationship between the size of the loop and the frequency measured from the carrier wave. In this figure, there are two There are standards. One is the dotted line marked 'IF response', which is the Manches line in Figure 1. A radio receiver (not shown) that can be used to receive signals using data output modulation schemes. (No) Toru. The second criterion is two straight lines with a 90° angle and one interference limit. It is marked as “International Specification”.

This is a typical wireless channel interference limit specification. These perpendicular lines Data points to the top and right of these lines have unacceptable interference; data points to the left and bottom of these lines The data points show that the interference is acceptable.

In Figure 2, the dashed line shows the continuous spectrum of the Hetzsell filter signal, approximately 35 It also contains energy at frequencies above kHz. The solid line indicates the ROM change according to the embodiment shown in FIG. This is a continuous spectrum of the conversion method. ■The right side of the F response standard also contains some energy. However, the energy in this region is much lower than that of a 10 kHz data rate. Below the curve, it contains somewhat more energy than the dashed curve. Therefore, the book The ROM conversion method according to the invention is based on the bandpass characteristics of the circuit that receives the data signal. It produces outputs that are numerically very well matched. This consistency improvement allows errors rate decreases.

Regarding interference, the data points indicated by stars in Figure 2 are the signals of the Hera cell filter type. the unmodulated carrier signal near the top of the ordinate axis; ] in the upper pressure part of the figure, contains a data signal component of 0 kHz. all other stars The marks are harmonics of the 1 kHz signal. Many of these harmonics, especially the 5th and 6th The harmonic frequencies of are close to the interference limit specifications, resulting in component fluctuations and small nonlinear modulations. 1, as opposed to , the corresponding ``X'' marks in the example of the ROM conversion method shown in Figure 1 are It shows the data points. This is found to be well below the interference limit specification. Ru.

Figures 3 to 6 show previous bit/current bit combinations, Sunawachi 0O101,1 In order to represent 2n 2-bit data strings of 11 colors, It shows four waveforms of stored data.

In all cases, the vertical axis has arbitrary amplitude units and is proportional to the current ROMI O output. do. The horizontal axis is time, which is expressed as a relative value from the starting point of the bit cell.

The starting point of such a bit cell is at the center on the axis, i.e. at the zero time position. There is. Therefore, the waveform in each figure is the waveform of the last half of the previous hitcell and the current waveform that follows. The waveform of the first half of the current bit cell is included. Therefore, each waveform is The data signal transition waveform between the bit cells of the data encoded signal, that is, from the 2nd to the 3rd time. The signal waveform shown in Figure 6 has three effects 4 have. One effect is the reproduction of data information. Only for bitcode conversion For that matter, the output waveform is similar to reproducing data information with a new bit code. You can choose anything arbitrarily. However, in the process of this conversion, the present invention both have the advantage of realizing one or more of two separate signal waveform modifications. There is. The second effect is the transition from 0 to 1 and from J in Figures 4 and 5, respectively. This is the effect of limiting the amplitude of the waveform on its transition to zero. These are as shown in the figure. The amplitude is limited to approximately ±110 amplitude units. In contrast, Fig. 3 and Fig. 6 00 The transition from to O and from l to 1 change by approximately ±125 amplitude units. , which undergoes greater attenuation in the radio receiving station's filter. Therefore, send By placing amplitude limits on the former two transitions in the station's encoding operation, Significantly less chance of having virtually the same data bit amplitude at any transition in the signal station Additionally, this allows the receiving station to avoid data transfer that depends on the data pattern. Width appearance can be reduced.

The third effect achieved by the ROM conversion type circuit in Figure 1 is a band limiting function. This eliminates the need to confine a large portion of the data signal to the radio device's passband. The above effects have been achieved. In addition, this method uses interference thickening at harmonics of the data rate. It also reduces the sharpness.

Although the present invention has been described with respect to particular embodiments thereof, other variations will be apparent to those skilled in the art. It goes without saying that other uses, embodiments, and modifications are included within the spirit and scope of the invention.

FI6.2 Frequency from carrier wave (~) Time relative to the start of the bit cell (in microseconds) Time relative to the start of the bit cell time (microseconds) of the bit cell relative to the start point of the bit cell (microseconds) Time (microseconds) relative to starting point International search report

Claims (1)

[Claims] 1 Output signal with a modified waveform corresponding to the data information content of the human data signal In a data signal processing device that generates signal waves, Let n be the number of states needed to define the content in the modified output signal wave. means for determining the state of n consecutive input data signal bits (e.g. 23.26. ), and configures the output signal waveform in response to the n states, and configures the output signal waveform in response to the n states. Combined signals using a clock that is faster than the highest frequency component of the input data signal A means for using a signal conversion function (for example, 10.27.30). A device that does this. 2. In the data signal processing device according to claim 1, means for shifting the input data signal with a delay of n bits; and configuring the n bits in the shifting means at each of the input data signal bit times. and means for coupling to the means for connecting. 3. In the data signal processing device according to claim 2, The configuring means further comprises: Accumulate multiple sets of 2n waveforms, each set representing each of the n states. It consists of different sets of the waveforms corresponding to different combinations of the waveforms, and the difference between the sets is The device is independent of the state and selects one of the sets. 4. In the data signal processing device according to claim 1, The configuring means further comprises: consisting of a different set of said waveforms corresponding to each different combination of said n states. comprising means for storing 2n waveforms; reading one of the sets in response to input data signal bit time combinations of the n states; A device characterized by emitting. 1 The storage means is configured to cancel distortion characteristics of a transmission medium through which the output signal waveform is to be sent. 2n such waveforms to which at least one of the waveforms is given a predetermined predistortion function; A device characterized by storing. 6. The device according to claim 1, wherein the human data signal is non-return to zero (N RZ) data signal, and the output waveform is the Manchester code of the NRZ data signal. data 18 that is a signal and r+ = 2 In the signal processing device, The storage means is configured to store bit intermediate signal transitions and bit intermediate signal transitions of the Manchester signal bit state, respectively. It is characterized by storing four waveforms representing some of the different pairs of cell-to-cell transitions. equipment. 7. In the data signal processing device according to claim 6, The four-waveform storage means cancels distortion characteristics of a transmission medium to which the output signal waveform is to be sent. #4 waveforms with a predetermined predistortion function added to at least one of the waveforms A device characterized by storing. 1 11 front entrance [0-501533 (2)