JPH0551215B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a serial data transmission device for serially transmitting digital data to a transmission line. [Prior Art] The transmission device shown in FIG. 6 is an example of an in-vehicle multiplex wiring system, and in the figure, 1 is a transmitter including a parallel/serial converter, 2 is a receiver including a serial/parallel converter, 3 is an input section such as a switch input, 4 is a load such as a lamp or motor, and 5 is a serial transmission line. The parallel data of the digital signal generated by the input section 3 is converted into digital serial data by a desired modulation method by the parallel/serial conversion section of the transmitting section 1, and is sent to the serial transmission line 5. The serial/parallel converter of the receiver 2 receives this serial data and converts it (demodulates) into parallel data.
Drive load 4. For example, the NRZ system shown in FIG. 7a is adopted as the format of the data sent from the transmitter 1. In the figure, after the idle state 6, a start bit (1 bit) 7 is sent out, followed by a predetermined number of bits (16 bits in the figure) of data bits 8,
Finally, stop bit 9 is sent out. The start bit 7 and data bit 8 correspond to one frame. FIG. 7b shows detection pulses for demodulating the serial data of FIG. 7a on the receiving side. In the figure, idle mode 6 ranges from H level (hereinafter described as "1") to L level (hereinafter described as "0").
The detection section provided in the serial/parallel converter 2 is activated at the timing when the start bit 7 changes.
After determining the data bit 8, the data bit 8 is determined sequentially. That is, if the time width of the basic clock of start bit 7 and data bit 8 is _T1 , the first detection pulse is output at the fall of idle state 6 from "1" to "0", and from this pulse _T1 The second detection pulse is output after /2. The information on the transmission line 5 is read at the time of the second detection pulse, and if it is "0", it is determined that the start bit 7 has been sent. After the second detection pulse, data bit 8 is detected with a time width of _T1 .
Detection pulses are output for the number of bits, and each state of data bit 8 is detected. In other words, the detection pulse is output at a timing of 1/2 of the basic clock width, and data bit 8 is detected. [Problems to be Solved by the Invention] In such a conventional transmission device, frame synchronization can be achieved using the start bit 7, but since bit synchronization cannot be achieved, the transmitting section and the receiving section each have independent basic clocks. Detection accuracy decreases due to frequency errors and fluctuations. The reason will be explained in detail below. The clock frequency on the transmitting side is f ₀ , the clock frequency on the receiving side is f ₁ ,
Assuming that 1 bit is 16 clocks, the period T ₁₆ of data bit 8 in FIG. 7a becomes T ₁₆ =16/f ₀ ×16. Further, the period T ₁₆ ' from the second detection pulse (detection of start bit 7) to the detection pulse of data bit 8 in FIG. 7b is T ₁₆ '=16/f ₁ ×16. Here, the limit 1 of the time difference between T ₁₆ and T ₁₆ ′
If 8/f ₀ corresponds to 50% variation in bits, then 8/f ₀ = T ₁₆ ′−T ₁₆ = 16/f ₁ ×16−16/f ₀ ×16, so f ₀ /f ₁ =1.03, Since the clock frequencies f ₀ and f ₁ on the transmitting and receiving sides are normally equal, a clock error of 3% or more causes a reception error on the receiving side. Also this
In the NRZ system, the number of data bits 8 following start bit 7 increases, and the longer the data length, the lower the tolerance for clock frequency error and the lower the detection accuracy. As described above, the conventional data transmission device has the following problems. (1) The allowable range of the independent basic clocks on the transmitting side and the receiving side is small, and the longer the data bit length, the smaller the allowable range is. (2) Therefore, the basic clock generating section is required to have high accuracy, but the structure is complicated and the cost is high.
The shape also becomes larger. (3) Since the detection pulse is driven by a change in the idle state (falling edge) and the subsequent start bit detection, it is susceptible to pulse noise. Therefore, in view of the above-mentioned conventional problems, the present invention includes independent clock generating sections in the transmitting section and the receiving section, and each data is generated based on the basic clock generated by the clock generating section of the transmitting section. 1”, “0”
Digital data of a predetermined number of bits consisting of information,
A serial data transmission device that serially transmits a synchronization bit indicating the start of the digital data and detects the synchronization bit and the data based on a basic clock generated by a clock generation section of the reception section. It is an object of the present invention to provide a serial data transmission device that widens the allowable range of independent basic clocks on the transmitting side and the receiving side without increasing costs, and is less susceptible to the influence of pulse noise. [Means for Solving the Problems] In order to achieve the above object, a serial data transmission device according to the present invention is provided with an independent clock generating section in a transmitting section and a receiving section, and a clock generating section of the transmitting section. Based on the basic clock that occurs,
Digital data of a predetermined number of bits, each data consisting of "1" and "0" information, and a synchronization bit indicating the start of the digital data are serially transmitted, and the basic clock generated by the clock generating section of the receiving section is used. In the serial data transmission device that detects the synchronization bit and the data based on the basic clock, the transmission section detects the synchronization bit and the "1" and "0" information of the data based on the basic clock.
Converts into pulse signals with different pulse widths, which are the H level time occupied in one bit time, and sends them out.
The receiving section detects the synchronization bit and the "1", "1", and
It is characterized by detecting "0" information so that the H levels have different patterns. [Operation] With the above configuration, the synchronization bit and the subsequent data bits "1" and "0" data are converted to have different pulse widths, so the serial data is converted into detection pulses with different time intervals. Therefore, it is demodulated by detecting the "1" and "0" information of the data bits and the synchronization bit, respectively. Therefore, the permissible frequency range of the basic clock on the transmitting and receiving sides is expanded. In addition, since the detection pulses are generated at different time intervals in synchronization with the rising edge of the signal that is the beginning of each bit, the error tolerance is constant regardless of the data length, and pulse noise The discharge function for such things will be improved. [Embodiments of the Invention] Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a transmission device according to the present invention, and in the figure, the transmitting side is composed of an input section 3 and a transmitting section 1. As shown in FIG. Furthermore, the transmitting section 1 is composed of a parallel/serial conversion circuit 25, a data controller 27, and a data generation circuit 28. The receiving side is composed of a load 4 and a receiving section 2, and the receiving section 2 includes a data detection circuit 40 and a sampling pulse generation circuit 4.
1 and a serial/parallel conversion circuit 52. Further, the transmitting section 1 and the receiving section 2 are coupled through a transmission path 5. In such a configuration, parallel data from the input section 3 is input to the parallel/serial conversion circuit 25 and converted into serial data. The converted serial data is processed by the data controller 27 into PWM with a predetermined modulation degree from the basic clock CK (frequency f 0 ) on the transmitting side, in which the synchronization bit (start bit) and the data bit "0" and " ₁ " information, which will be described later, are converted into PWM signals.
(pulse width modulation) modulated. The PWM modulated transmission data is input to the data generation circuit 28, and sent to the transmission line 5 at the timing of the basic clock CK on the transmitting side. The receiving section 2 inputs the transmission data on the transmission path 5 to the data detection circuit 40. The sampling pulse generation circuit 41 generates sampling pulses at predetermined intervals according to the timing of the basic clock (frequency f ₁ ) on the receiving side, and the data detection circuit 40 samples the transmission data using the pulses, and detects the synchronization bits and data of the transmission data. Bit "0" or "1" information is sequentially detected. The detected data is converted into parallel data by a serial/parallel conversion circuit 52 to drive the load 4. FIG. 2 is a waveform diagram of transmission data sent to the transmission line according to the present invention, and is one frame (period T _F ).
is 1 bit synchronization bit (start bit) 7,
Data bits 8 (16 bits in the example), and 1
It consists of a total of 18 bits (10 parity bits). Note that the parity bit 10 may not be provided. In such transmission data, the time for 1 bit is
T _BIT is 32 clocks of the basic clock, the pulse width T _syoc of synchronization bit 7 is 28 clocks, the pulse width T ₀ of data “0” of data bit 8 is 8 clocks, and the pulse width T ₁ of data “1” is 8 clocks. is set to 16 clocks. That is, when the frequency of the basic clock is f ₀ , the time T _BIT of 1 bit is T _BIT = 32/f ₀ ×n (n = 1 or 2), and the pulse width T _syoc of synchronization bit 7 is T _syoc =28/f ₀ n Pulse width of data “0” among data bits 8
T ₀ is T ₀ =8/f ₀ n , and the pulse width T ₁ of data “1” is T ₁ =16/f ₀ n . In other words, the synchronization bits and data bits are each pulse width modulated (PWM) with different modulation depths.
has been done. Figures 3a to 3d show timing charts for detecting and demodulating the transmission data of Figure 2 on the receiving side;
The waveforms of one bit each of data "1" and data "0" of synchronization bit 7 and data bit 8 in the figure are shown, and d in the figure shows a sampling pulse signal in the receiving section. Each synchronization bit 7, data bit 8
The counter of the receiving section is started at the rise of the signal from the L level to the H level, and the first pulse signal is output at the timing of the rise. The sampling pulse signals are generated in the following order: S ₁ →S ₂ →S ₃ . Each pulse signal
S ₁ , S ₂ , and S ₃ sample the transmission data at that timing and detect the H level or L level. Time t ₁ from the first pulse S ₀ to S ₁ , S ₂ , S ₃ ,
t ₂ and t ₃ are 5 clocks each of the basic clock of the receiving section,
They are 12 clocks and 22 clocks. That is, if the basic clock frequency of the receiving section is f ₁ , the time t ₁ is t ₁ = 5/f ₁ × n (n = 1 or 2), and t ₂ and t ₃ are each t ₂ = 12/f ₁ ×nt ₃ =22/f ₁ ×n. Note that the transmitting and receiving clock frequencies f ₀ and f ₁ are usually set equal. Sampling pulse signal S ₁ ,
The H level or L level detected in S ₂ and S ₃ is “1” or “0” of synchronization bit 7 and data bit 8.
Each information is set as shown in the truth table shown in Table 1.

〔Effect of the invention〕

As described above, according to the present invention, the error tolerance between the basic clock frequencies on the transmitting side and the receiving side can be greatly improved. Furthermore, since the transmitted data is of a synchronous bit type, the error tolerance is constant regardless of the data length. Therefore, the ability to eliminate pulse noise and the like is improved, and the quality of transmitted data is improved. Furthermore, since the error tolerance is large, the oscillator for obtaining the basic clock does not need to be highly accurate, and the oscillator can be constructed easily and inexpensively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the serial data transmission device according to the present invention, FIG. 2 is a waveform diagram of serial data sent to the transmission line in the device shown in FIG. 4 and 5 are block diagrams showing the specific configurations of the transmitter and receiver in FIG. 1, respectively;
FIG. 6 is a block diagram showing a conventional data transmission device, and FIGS. 7a and 7b are waveform diagrams of data sent to the transmission line in the device of FIG. 6 and waveform diagrams of sampling detection pulses on the receiving side. 1... Transmission section, 2... Receiving section, 5... Transmission path,
7...Synchronization bit, 8...Data bit, 20...
...Frequency divider circuit, 21...Write enable generation circuit, 22...Frame counter, 23...Input/
Output wire, 24... Latch circuit, 25... Shift register, 26... Parity generation circuit, 27
... Data controller, 28 ... Data generation circuit, 29 ... Data set signal, 30 ... Shift pulse signal, 31 ... Input data, 40 ... Data detection circuit, 41 ... Sampling clock & shift pulse generation circuit , 42...Error output generation circuit, 43...Latch prohibition signal, 44...Parity check circuit, 45...Latch control circuit, 46...Latch timing generation circuit, 47...
...sampling signal, 48...reception error signal,
49...Latch signal, 50...Data.

Claims (1)

[Scope of Claims] 1. The transmitting section and the receiving section are provided with independent clock generating sections, and each data is set to "1" or "0" based on a basic clock generated by the clock generating section of the transmitting section.
Digital data of a predetermined number of bits consisting of information,
In a serial data transmission device that serially transmits a synchronization bit indicating the start of the digital data and detects the synchronization bit and the data based on a basic clock generated by a clock generation section of the reception section, the transmission section comprises: , based on the basic clock,
The synchronization bit and the "1" and "0" information of the data are converted into pulse signals having different pulse widths, which are the H level time occupied in one bit time, and sent out, and the receiving section receives the pulse signals. In response to the rise of the signal from L to H level, detection clocks with different time intervals created based on the basic clock are used to detect the synchronization bit and the data "1",
1. A serial data transmission device that detects "0" information such that H levels have different patterns.