JP5987371B2 - Data receiving circuit, electronic device, and data receiving method - Google Patents

Description

  The present invention relates to a data receiving circuit, an electronic device, a data receiving method, and the like.

  In recent years, with the increase in screen size, resolution, 3D, etc. of display panels such as liquid crystal panels and organic EL (Electro-Luminescence) panels, the transfer frequency of display data supplied to the display driver that drives the display panel has increased. It has increased dramatically. Therefore, it is necessary to cope with the problem by widening the bus width to which display data is transferred, or by further increasing the data transfer frequency of display data.

  However, when a bus to which display data is transferred is driven by a buffer composed of CMOS (Complementary Metal Oxide Semiconductor), if the bus width is widened, there is a problem that EMI (Electro Magnetic Interface) noise and power supply fluctuation increase. is there. Thus, display data is often transferred using a differential interface technology such as LVDS (Low Voltage Differential Signaling) or Mini-LVDS.

  However, even if this differential interface technology such as LVDS or Mini-LVDS is used, it is necessary to further increase the frequency, and the waveform of the clock differential signal and the data differential signal also at the currently required frequency. There is a problem that a shift occurs. For this reason, recently, display data may be transferred using SerDes in which a clock and data are embedded in a differential signal and various interface technologies improved from this.

  On the other hand, data obtained by modulating a clock and display data by pulse width modulation is also transmitted through a transmission line. For example, Patent Literature 1 and Patent Literature 2 disclose a technique for transmitting data obtained by modulating a clock and data by pulse width modulation via a transmission line.

JP 2007-129735 A US Pat. No. 6,463,092

  However, with the above-mentioned SerDes (Serializer / Deserializer) and improved interface technology, the data transfer frequency has reached the limit of the measuring device, making it difficult to compensate the performance by measuring the measuring device. ing. In addition, these interface technologies have a problem in that a PLL (Phased-Locked Loop) circuit is required not only on the transmission side but also on the reception side for each differential signal line. Further, the scale of the logic circuit such as restoring the clock from the data becomes large. For example, in a display driver that requires a long chip shape and multiple outputs, the display driver becomes large in the short side direction, resulting in high costs and mounting problems. .

  Further, as disclosed in Patent Document 1 and Patent Document 2, even when data is simply transmitted by pulse width modulation, if there is no PLL circuit on the receiving side as well as on the transmitting side, there are many high frequencies. There is a problem that it is difficult to cope with bit conversion.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or modes.

  (1) According to a first aspect of the present invention, a data receiving circuit that receives data modulated by pulse width modulation having two or more types of step widths, a data delay unit that delays the data, and the data delay unit A capture timing generation unit that sequentially delays the output of the plurality of capture timings to generate a plurality of capture timings having two or more step sizes, and a plurality of capture timings generated by the capture timing generation unit, A data capture unit that captures data; and a reception data detection unit that detects reception data based on captured data captured at each capture timing in the data capture unit.

  In this aspect, the output of the data delay unit that delays data modulated by pulse width modulation having two or more types of step widths is sequentially delayed to generate the capture timing corresponding to the step size. As a result, multi-bit pulse width modulated data can be received on the receiving side without providing a PLL circuit, so that multi-bit pulse width modulation can be realized. Thereby, it can contribute to size reduction of an integrated circuit provided with the data receiving circuit in this mode.

  (2) In the data reception circuit according to the second aspect of the present invention, in the first aspect, the plurality of capture timings have smaller step sizes as the capture timing is closer to the reference timing.

  In this aspect, a plurality of capture timings are generated so that the step size becomes smaller as the capture timing is closer to the reference timing. For example, the reference timing can be a data change timing (specifically, a rising edge). Thereby, for example, when the plurality of capture timings are generated by delaying the reference timing, the step size can be defined by the delay accuracy from the reference timing. Therefore, data can be captured at each capture timing defined with high precision regardless of the timing difference between the reference timing and each capture timing. As a result, for example, when detecting the H level width of the pulse width modulated data with reference to the rising edge of the data, a plurality of capture timings are generated by a simple delay circuit within a limited period. This makes it possible to increase the number of bits of pulse width modulation.

  (3) In the data reception circuit according to the third aspect of the present invention, in the first aspect, the plurality of capture timings have a larger step size as the capture timing is closer to the reference timing.

  In this aspect, a plurality of capture timings are generated so that the step size becomes larger as the capture timing is closer to the reference timing. For example, the reference timing can be a data change timing (specifically, a rising edge). Thereby, for example, when the plurality of capture timings are generated by delaying the reference timing, the step size can be defined by the delay accuracy from the reference timing. Therefore, data can be captured at each capture timing defined with high precision regardless of the timing difference between the reference timing and each capture timing. As a result, when the width of the L level of the pulse width modulated data is detected with reference to the rising edge that is the end timing of the L level fixed period of the pulse width modulated data, a larger number of data are detected within the limited period. Can be generated by a simple delay circuit, and the number of bits of pulse width modulation can be increased.

  (4) In the data reception circuit according to the fourth aspect of the present invention, in any one of the first aspect to the third aspect, the data capture unit corresponds to each of the plurality of capture timings. A plurality of flip-flops that are provided and initialized prior to the reception of the data, and each of the plurality of flip-flops captures the predetermined data based on a capture clock that changes at a corresponding capture timing .

  According to this aspect, the pulse width of the data can be detected by the flip-flop in which the retained data is predetermined data and the flip-flop in which the retained data is the initial value among the plurality of flip-flops. become.

  (5) In the data reception circuit according to the fifth aspect of the present invention, in any one of the first to fourth aspects, a control value corresponding to a power supply voltage of the data delay unit is set. Including a delay setting register, and sets the power supply voltage of the data delay unit to a voltage corresponding to the control value set in the first delay setting register.

  According to this aspect, since the data delay value is adjusted by changing the power supply voltage of the data delay unit, the capture timing can be adjusted with a very simple configuration and control.

  (6) A data reception circuit according to a sixth aspect of the present invention is provided between the data delay unit and the capture timing generation unit in any one of the first to fifth aspects, An output buffer for buffering the output of the data delay unit and then outputting to the capture timing generation unit; and a second delay setting register for setting a control value corresponding to the power supply voltage of the output buffer, The power supply voltage of the output buffer is set to a voltage corresponding to the control value set in the second delay setting register.

  According to this aspect, since the data delay value is adjusted by changing the power supply voltage of the output buffer connected to the output of the data delay unit, the capture timing can be adjusted with a very simple configuration and control. Can be adjusted.

  (7) In the data reception circuit according to the seventh aspect of the present invention, in any one of the first aspect to the sixth aspect, each of the capture timing generation units is configured by a resistance element and a capacitance element. Each of the plurality of delay circuits is connected in cascade, and the output of each delay circuit is output as each capture timing.

  According to this aspect, since each of the plurality of delay circuits is connected in cascade and the output of each delay circuit is output as the capture timing, the multi-bit pulse width modulation can be achieved with the delay circuit having a simple configuration. Can be provided.

  (8) According to an eighth aspect of the present invention, there is provided a data receiving circuit according to the seventh aspect, wherein a plurality of clock buffers each connected to an output of a corresponding delay circuit and a power supply voltage of the plurality of clock buffers are used. And a third delay setting register in which a corresponding control value is set, and the power supply voltages of the plurality of clock buffers are set to voltages corresponding to the control value set in the third delay setting register.

  According to this aspect, since the power supply voltage of the clock buffer that outputs the capture clock corresponding to each capture timing is changed, the capture timing can be adjusted with a very simple configuration and control. .

  (9) In the data reception circuit according to the ninth aspect of the present invention, in the seventh aspect or the eighth aspect, a termination circuit connected to termination units of the plurality of delay circuits, and a capacitance value of the termination circuit And a fourth delay setting register in which a control value corresponding to is set, and the capacitance value of the termination circuit is set to a capacitance value corresponding to the control value set in the fourth delay setting register.

  According to this aspect, since the delay value of the data is adjusted by changing the capacitance value of the termination circuit connected to the termination units of the plurality of delay circuits, the data can be obtained with a very simple configuration and control. Can be adjusted.

  (10) In the data receiving circuit according to the tenth aspect of the present invention, in any of the seventh aspect to the ninth aspect, a control value corresponding to the capacitance value of the capacitive element constituting the delay circuit is set. And a capacitance value of the capacitive element is set to a capacitance value corresponding to the control value set in the fifth delay setting register.

  According to this aspect, since the delay value of the data is adjusted by changing the capacitance value of the capacitive element that constitutes each of the plurality of delay circuits, the capture timing can be adjusted with a very simple configuration and control. Can be adjusted.

  (11) A data receiving circuit according to an eleventh aspect of the present invention is the data receiving circuit according to any one of the seventh aspect to the tenth aspect, wherein each of the plurality of delay circuits is set prior to output of the corresponding capture timing. A capacitor initialization circuit is included that initializes the electric charge charged in the capacitor element.

  According to this aspect, even when data is repeatedly received, the plurality of delay circuits can delay the capture timing with high accuracy.

  (12) In a twelfth aspect of the present invention, an electronic device includes the data receiving circuit according to any one of the first to eleventh aspects.

  According to this aspect, it is possible to provide an electronic device capable of transmitting and receiving a large amount of data at high speed at a low cost even when the frequency exceeds the measurement limit of the measuring device without providing a PLL circuit on the receiving side. Can contribute.

  (13) In a thirteenth aspect of the present invention, a data reception method for receiving data modulated by pulse width modulation having two or more types of step widths is determined based on a reference timing corresponding to the data change timing. A data capture step for capturing the data at a plurality of capture timings having two or more step sizes, and received data based on the capture data captured at the plurality of capture timings in the data capture step And a received data detecting step for detecting.

  In this aspect, the capture timing is generated based on the reference timing corresponding to the change timing of the data modulated by the pulse width modulation having two or more types of step widths. As a result, multi-bit pulse width modulated data can be received on the receiving side without providing a PLL circuit, so that multi-bit pulse width modulation can be realized.

  (14) A data reception method according to a fourteenth aspect of the present invention includes, in the thirteenth aspect, a capture timing generation step of generating the plurality of capture timings by sequentially delaying the reference timing, The plurality of capture timings have smaller increments as the capture timing is closer to the reference timing.

  In this aspect, a plurality of capture timings are generated so that the step size becomes smaller as the capture timing is closer to the reference timing. For example, the reference timing can be a data change timing (specifically, a rising edge). Thereby, the step size can be defined by the delay accuracy from the reference timing, and data can be captured at each capture timing that is defined accurately regardless of the timing difference between the reference timing and each capture timing. As a result, a plurality of capture timings can be generated by simple delay means within a limited period, and multi-bit pulse width modulation can be achieved.

  (15) The data receiving method according to a fifteenth aspect of the present invention is the data receiving method according to the fourteenth aspect, wherein at least one of the power supply voltage of the delay means for delaying the reference timing and the capacitance value of the capacitive element constituting the delay means The capture timing generation step generates the plurality of capture timings by sequentially delaying the reference timing by the delay means adjusted in the delay adjustment step.

  According to this aspect, a plurality of capture timings can be generated with a simple configuration and control.

  (16) In the data reception method according to the sixteenth aspect of the present invention, in the fifteenth aspect, the delay adjustment step includes: the first data having the shortest pulse width of the data; and the pulse width of the data The delay value of the delay means is adjusted using the longest second data.

  According to this aspect, since the delay value of the delay means is adjusted using the first data having the shortest pulse width and the second data having the longest pulse width, the number of steps is very small. The capture timing corresponding to a plurality of step sizes can be adjusted.

1 is a block diagram of a configuration example of an electronic device to which a data receiving circuit according to a first embodiment is applied. Explanatory drawing of the pulse width modulation in 1st Embodiment. FIG. 2 is a block diagram of a configuration example of a data receiving circuit according to the first embodiment. The figure which shows the outline | summary of a structure of a delay control register. The flowchart of the operation example of the data receiving circuit in 1st Embodiment. FIG. 4 is a circuit diagram of a detailed configuration example of the data receiving circuit of FIG. 3. FIG. 4 is a circuit diagram of a configuration example of the pulse width detection circuit of FIG. 3. The figure which shows an example of the simulation result of the data receiver circuit in 1st Embodiment. The figure which shows the other example of the simulation result of the data receiving circuit in 1st Embodiment. The block diagram of the structural example of the data receiving circuit in 2nd Embodiment. The figure which shows the outline | summary of a structure of a timing adjustment control register. The flowchart of the operation example of the timing adjustment control in 2nd Embodiment. The flowchart of the operation example of the timing adjustment control in 2nd Embodiment. The figure which shows the structural example of the delay circuit in the modification of 1st Embodiment or 2nd Embodiment. FIG. 3 is an explanatory diagram of display data supplied from the display data supply device of FIG. 1 to a display driver. FIGS. 16A and 16B are perspective views illustrating a configuration of an electronic device having a display driver including a data reception circuit according to the first embodiment, the second embodiment, or a modification example thereof.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, all of the configurations described below are not necessarily indispensable configuration requirements for solving the problems of the present invention.

[First Embodiment]
FIG. 1 shows a block diagram of a configuration example of an electronic device to which a data receiving circuit according to the first embodiment of the present invention is applied.

  The electronic device 10 includes a display data supply device 20, a display driver 30, and a display panel 40. The display data supply device 20 includes a display data generation circuit 22, a data transmission circuit 24, a PLL circuit 26, and a transmission control unit 28. The display driver 30 includes a data receiving circuit 100 and a driving circuit 32. The function of the display data supply device 20 is realized by, for example, a so-called display controller or a central processing unit. The display panel 40 is a liquid crystal panel or an organic EL panel in which a plurality of pixels are arranged in a matrix. The display driver 30 drives the pixels constituting the display panel 40 based on the display data supplied from the display data supply device 20, and displays an image corresponding to the display data.

  In the display data supply device 20, the display data generation circuit 22 generates display data corresponding to an image displayed on the display panel 40. The PLL circuit 26 generates a clock corresponding to the step width of the pulse width modulation in the first embodiment and outputs it to the data transmission circuit 24. The data transmission circuit 24 performs a process of performing pulse width modulation on the display data generated by the display data generation circuit 22 using the clock from the PLL circuit 26 and transmitting the data after the pulse width modulation to the display driver 30. Do. Specifically, the data transmission circuit 24 performs pulse width modulation by modulating the change timing of transmission data with display data. The transmission control unit 28 controls the display data generation circuit 22, the data transmission circuit 24, and the PLL circuit 26.

  In the display driver 30, the data receiving circuit 100 performs processing for receiving data transmitted by the display data supply device 20. The data receiving circuit 100 detects the received data corresponding to the change timing of the received data based on the step width of the pulse width modulation in the first embodiment, and the detected received data is sent to the drive circuit 32 as the received display data. Output. The drive circuit 32 drives the display panel 40 based on the data received by the data receiving circuit 100.

  FIG. 2 shows an explanatory diagram of pulse width modulation in the first embodiment. FIG. 2 shows an example in which pulse width modulation is performed on 4-bit display data in one cycle period.

  In the received data subjected to the pulse width modulation in the first embodiment, the rising edge of the data is extracted as the reference timing, and one cycle period is defined. A predetermined H level fixing period t0 that is always fixed to the H level is provided at the beginning of one cycle period, and a predetermined L level fixing period t1 that is always fixed to the L level is provided at the end of one cycle period. It is done. In the received data, 15 falling edge positions are defined in two or more step sizes within a period excluding the H level fixed period t0 and the L level fixed period t1 within one cycle period. Including the positions of the falling edges where the H level fixed period t0 ends, the positions of 16 falling edges are defined within one cycle period.

The position of each falling edge corresponds to each of 4-bit display data. For example, the position of the falling edge after the period t0 with respect to the reference timing corresponds to the display data “(0) ₁₆ ” (= (0000) ₂ ). Further, the position of the falling edge after the “t0 + tw ₀ ” period in which the step width tw ₀ has elapsed after the t0 period corresponds to the display data “(1) ₁₆ ” (= (0001) ₂ ). Similarly, the position of the falling edge after the “t0 + tw ₀ + tw ₁ ” period with reference to the reference timing corresponds to the display data “(2) ₁₆ ” (= (0010) ₂ ). Then, the position of the falling edge after the “t0 + tw ₀ + tw ₁ +... + Tw ₁₅ ” period with reference to the reference timing corresponds to the display data “(F) ₁₆ ” (= (1111) ₂ ).

In the first embodiment, the position of each falling edge is defined so that the step size becomes coarser as the distance from the reference timing increases. That is, 0 <tw ₁ <tw ₂ <tw ₃ <... <Tw ₁₄ <tw ₁₅ . Specifically, in the first embodiment, when the reference timing is delayed to define each step size and k is a real number of 1 or more, the following equation is established. k is determined according to the delay accuracy when the timing of each falling edge is defined by delaying the timing of the immediately preceding falling edge.

  Here, it is assumed that the position of the falling edge of the received data is defined by sequentially delaying the reference timing without using a complicated circuit such as a PLL circuit. At this time, if the positions of 16 falling edges are defined with equal step sizes within a period excluding the H level fixed period t0 and the L level fixed period t1, the falling edge becomes farther from the reference timing. Fluctuation increases. That is, the position of the falling edge close to the reference timing can be accurately defined, while the position of the falling edge far from the reference timing cannot be accurately defined due to element variation or the like.

  On the other hand, in the first embodiment, the position of each falling edge is defined so that the step size becomes coarser as the distance from the reference timing increases. Therefore, the position of the falling edge close to the reference timing can be accurately defined because the fluctuation is small. Further, the position of the falling edge that is far from the reference timing has a large step size, so that the position of the falling edge can be reliably defined even if there is element variation.

  As described above, according to the first embodiment, the reference timing extracted from the reception data can be sequentially delayed to generate the capture timing of each falling edge. Therefore, without providing a PLL circuit, The position of the falling edge can be accurately defined. As a result, it is possible to realize multi-bit pulse width modulation.

  By the way, it is said that the measurement of a signal of 200 MHz is the limit for the current measuring equipment in consideration of measurement variation. In contrast, in the first embodiment, a case is considered in which 4-bit display data is transferred at a transfer frequency of 400 MHz in one cycle period of 10 ns (= 4 × 2.5 ns). Assuming that each of the H level fixed period t0 and the L level fixed period t1 is 1.25 ns, it is only necessary to define 15 steps in the remaining 7.5 ns. That is, even if the step size is defined uniformly, 0.5 ns can be assigned to one step size. With a 0.5 ns step size, it is possible to accurately measure multi-bit pulse-width-modulated data even with current measurement equipment having a measurement variation of about 62.5 ps. As described above, according to the first embodiment, even at a frequency exceeding the measurement limit of the measuring device, it is possible to transmit and receive a large amount of display data at high speed at a low cost.

  FIG. 3 is a block diagram illustrating a configuration example of the data receiving circuit 100 according to the first embodiment. FIG. 3 shows a configuration example in the case of receiving reception data in which 4-bit display data is modulated by pulse width modulation having different step sizes. FIG. 3 shows a configuration in which data is captured at the positions of more than 16 falling edges for the purpose of error detection or the like, but data is captured at the positions of 16 falling edges at the minimum. If you can.

  The data receiving circuit 100 includes a delay circuit (data delay unit) 110, an output buffer 120, a capture timing generation circuit (capture timing generation unit) 130, a data capture circuit (data capture unit) 140, a pulse A width detection circuit (reception data detection unit) 150. Further, the data receiving circuit 100 includes a delay control register 160 and a delay control circuit 180.

  The delay circuit 110 delays the reception data D from the display data supply device 20. The delay circuit 110 has a configuration in which one or a plurality of delay elements are connected in cascade, and is configured such that the power supply voltage of each delay element can be changed. Therefore, the edge of the change point of the reception data D can be made sharp by setting the power supply voltage of the delay circuit 110 high, and the change point of the reception data D can be set by setting the power supply voltage of the delay circuit 110 low. Edges can be blunted.

  The output buffer 120 is provided between the delay circuit 110 and the capture timing generation circuit 130, buffers the output of the delay circuit 110, and outputs the buffered received data to the capture timing generation circuit 130. The power supply voltage of the output buffer 120 can be changed. Therefore, by setting the power supply voltage of the output buffer 120 high, the edge of the change point of the reception data can be made sharp, and by setting the power supply voltage of the output buffer 120 low, the edge of the change point of the reception data Can be slowed down.

  The capture timing generation circuit 130 sequentially delays the output of the output buffer 120 (or the delay circuit 110) to generate a plurality of capture timings having two or more types of step sizes. The plurality of capture timings have smaller increments as the capture timing is closer to the reference timing. The capture timing generation circuit 130 includes a plurality of delay circuits DC0 to DC19, a termination circuit 132, and a plurality of clock buffers CB0 to CB19.

  The output of the output buffer 120 is connected to the input of the delay circuit DC0, each of the delay circuits DC0 to DC19 is connected in cascade, and the output of each delay circuit becomes each capture timing. A termination circuit 132 is connected to the output of the delay circuit DC19 in the final stage of the delay circuits DC0 to DC19 connected in cascade. The delay values of the delay circuits DC0 to DC19 are configured to be adjustable. The capacitance value of the termination circuit 132 is configured to be adjustable. The termination circuit 132 has a function of absorbing reflections of signals propagating through the delay circuits DC0 to DC19, and the delay value of each capture timing can be adjusted by changing the capacitance value.

  Each input of the plurality of clock buffers CB0 to CB19 is connected to the output of the corresponding delay circuit, and each of the plurality of clock buffers CB0 to CB19 takes in the capture clocks CL0 to CL19 corresponding to the capture timing. Output to circuit 140. Each power supply voltage of the plurality of clock buffers CB0 to CB19 can be changed. Therefore, by setting the power supply voltage of the clock buffers CB0 to CB19 high, the edges of the transition points of the fetch clocks CL0 to CL19 can be made steep. By setting the power supply voltage of the clock buffers CB0 to CB19 low, the edges of the transition points of the capture clocks CL0 to CL19 can be blunted.

  The data capture circuit 140 captures predetermined data at a plurality of capture timings generated by the capture timing generation circuit 130. That is, the data capture circuit 140 includes a plurality of flip-flops provided corresponding to each of a plurality of capture timings, and each flip-flop is predetermined based on a capture clock that changes at the corresponding capture timing. Import the data. Each flip-flop is initialized prior to reception of reception data D. For example, the predetermined data is H level data, and the flip-flop after initialization holds L level data. By doing so, the data fetch circuit 140 holds the H level data only in the flip-flops to which the fetch clock that changes to the H level among the fetch clocks CL0 to CL19 is input. The flip-flop to which the capture clock that remains at the L level is input retains the L level data. Captured data DL <b> 0 to DL <b> 19 captured by the data capture circuit 140 is output to the pulse width detection circuit 150.

  The pulse width detection circuit 150 detects received data based on the captured data DL0 to DL19. Specifically, the pulse width detection circuit 150 detects the reception data corresponding to the detected pulse width by detecting the pulse width based on the acquisition data DL1 to DL16, and based on the acquisition data DL0 and DL17. An error is detected and an error detection result signal ERR is output. The reception data RD detected by the pulse width detection circuit 150 is supplied to the drive circuit 32 of the display driver 30.

  The delay control register 160 has a control for controlling at least one of the delay circuit 110, the output buffer 120, the delay circuits DC0 to DC19, the clock buffers CB0 to CB19, and the termination circuit 132 that constitute the capture timing generation circuit 130. Value is set.

  FIG. 4 shows an outline of the configuration of the delay control register 160. The delay control register 160 is a register that can be accessed by the display data supply device 20 or a CPU (not shown) (hereinafter, the display data supply device 20 or the like).

  The delay control register 160 includes a delay circuit control register 162, an output buffer control register 164, a capacitance value control register 166, a clock buffer control register 168, and a termination circuit control register 170.

  In the delay circuit control register 162, a control value corresponding to the power supply voltage of the delay circuit 110 is set as the first delay setting register by the display data supply device 20 or the like. The delay control circuit 180 outputs a control signal C1 corresponding to the control value set in the delay circuit control register 162, and sets the power supply voltage of the delay circuit 110 to a voltage corresponding to the control value.

  In the output buffer control register 164, as the second delay setting register, a control value corresponding to the power supply voltage of the output buffer 120 is set by the display data supply device 20 or the like. The delay control circuit 180 outputs a control signal C2 corresponding to the control value set in the output buffer control register 164, and sets the power supply voltage of the output buffer 120 to a voltage corresponding to the control value.

  In this way, the delay value can be adjusted independently for each of the delay circuit 110 and the output buffer 120. Thereby, for example, the delay value can be adjusted largely by the delay circuit 110, and the reception data having a sufficient amplitude level can be supplied to the capture timing generation circuit 130 by the output buffer 120.

  In the capacitance value control register 166, a control value corresponding to the delay values of the delay circuits DC0 to DC19 is set as the fifth delay setting register by the display data supply device 20 or the like. Specifically, the capacitance value control register 166 is set with a control value corresponding to the capacitance value of the capacitive element constituting each of the delay circuits DC0 to DC19. The delay control circuit 180 outputs a control signal C3 corresponding to the control value set in the capacitance value control register 166, and simultaneously sets the capacitance value constituting each of the delay circuits DC0 to DC19 to the capacitance value corresponding to the control value. Set to.

  In the clock buffer control register 168, a control value corresponding to the power supply voltage of the clock buffers CB0 to CB19 is set as a third delay setting register by the display data supply device 20 or the like. The delay control circuit 180 outputs a control signal C4 corresponding to the control value set in the clock buffer control register 168, and simultaneously sets the power supply voltages of the clock buffers CB0 to CB19 to voltages corresponding to the control value.

  In the termination circuit control register 170, a control value corresponding to the capacitance value of the termination circuit 132 is set as the fourth delay setting register by the display data supply device 20 or the like. The delay control circuit 180 outputs a control signal C5 corresponding to the control value set in the termination circuit control register 170, and sets the capacitance value of the termination circuit 132 to a capacitance value corresponding to the control value.

  As described above, in the pulse width modulation in the first embodiment, the rising edge of the received data is extracted as the reference timing. The reference timing is sequentially delayed by the delay circuit 110, the output buffer 120, the plurality of delay circuits DC0 to DC19, the clock buffers CB0 to CB19, and the termination circuit 132, and is generated as a capture clock corresponding to the capture timing. Each of the delay circuit 110, the output buffer 120, the plurality of delay circuits DC0 to DC19, the clock buffers CB0 to CB19, and the termination circuit 132 is configured to be able to adjust the delay value. Therefore, the capture timing and the capture clock corresponding to this can be adjusted.

  FIG. 5 shows a flowchart of an operation example of the data receiving circuit 100 according to the first embodiment.

  First, in the data receiving circuit 100, the display data supply device 20 or the like sets a control value in each register constituting the delay control register 160 and adjusts the delay value (step S1, delay adjustment step). For example, the display data supply device 20 or the like repeatedly sets the control value in each register and verifies the detection result of the pulse width detection circuit 150. As a result, the optimum delay values of the delay circuit 110, the output buffer 120, the delay circuits DC0 to DC19, the clock buffers CB0 to CB19, and the termination circuit 132 are determined.

  Next, the data receiving circuit 100 waits for data reception from the display data supply device 20 (step S2: N).

  When data from the display data supply device 20 is received (step S2: Y), the data reception circuit 100 generates a capture timing based on the received data input via the output buffer 120 (step S3, Capture timing generation step). Specifically, the data reception circuit 100 generates the capture timing by sequentially delaying the rising timing of the received data in the capture timing generation circuit 130. At this time, the capture timing generation circuit 130 outputs capture clocks CL0 to CL19 corresponding to the capture timing to the data capture circuit 140.

  Subsequently, the data receiving circuit 100 captures the H level data based on the capture clocks CL0 to CL19 in the plurality of flip-flops constituting the data capture circuit 140 (step S4, data capture step). The data capture circuit 140 outputs the data latched by the plurality of flip-flops to the pulse width detection circuit 150 as capture data DL0 to DL19.

  Thereafter, the data receiving circuit 100 detects the received data in the pulse width detection circuit 150 based on the captured data DL0 to DL19 captured by the data capturing circuit 140 at a plurality of capture timings (step S5, received data). Detection step). Thereafter, the data receiving circuit 100 ends a series of processing (end).

  FIG. 6 shows a circuit diagram of a detailed configuration example of the data receiving circuit 100 of FIG. In FIG. 6, the pulse width detection circuit 150, the delay control register 160, and the delay control circuit 180 in FIG. 3 are not shown. In FIG. 6, the same parts as those in FIG.

  The delay circuit 110 includes a plurality of buffers connected in cascade, and the power supply voltage of each buffer is set to a voltage set by the control signal C1.

  The capture timing generation circuit 130 includes a capacity initialization circuit 134 in addition to the delay circuits DC0 to DC19, the termination circuit 132, and the clock buffers CB0 to CB19.

  The delay circuit DC0 includes a resistive element having one end connected to the output of the output buffer 120 and the other end connected to one electrode of the capacitive element, and the capacitive element having the other electrode grounded. The other end of this resistance element is connected to the delay circuit DC1 at the next stage and to the input of the corresponding clock buffer CB0. The capacitive element constituting the delay circuit DC0 is a varactor diode, and is an element whose capacitance value is variable by changing the junction capacitance by a reverse bias voltage applied between the anode and the cathode. The capacitance value of this capacitive element is set by the control signal C3. Each of the delay circuits DC0 to DC19 has the same configuration.

  The termination circuit 132 includes a resistance element having one end connected to the output of the delay circuit DC19 and the other end connected to one electrode of the capacitance element, and the capacitance element having the other electrode grounded. This capacitive element is a varactor diode, and its capacitance value is set by a control signal C5.

  Capacitance initialization circuit 134 initializes the charges charged in the capacitive elements constituting each of delay circuits DC0 to DC19 prior to the output of each capture timing by capture timing generation circuit 130. Such a capacitance initialization circuit 134 includes a plurality of N-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) provided corresponding to the capacitive elements constituting each of the delay circuits DC0 to DC19. The source of each MOSFET is grounded, and the drain is connected to one electrode of the capacitive element constituting the corresponding delay circuit. A signal obtained by logically inverting the output of the delay circuit 110 is supplied to the gate of each MOSFET, and the MOSFET is turned on at the L level before the rising timing of the reception data D. As a result, the delay circuits DC0 to DC19 can delay the capture timing with high accuracy even when received data is repeatedly input.

  The data fetch circuit 140 includes flip-flops DF0 to DF19. Each of the flip-flops DF0 to DF19 includes a data input terminal D, a clock input terminal C, a data output terminal Q, and a reset input terminal R. The clock input terminal C of each of the flip-flops DF0 to DF19 is input with a clock taken in from the corresponding clock buffer. A high potential side power source is connected to each data input terminal D of the flip-flops DF0 to DF19. Each of the flip-flops DF0 to DF19 takes in the H level data inputted to the data input terminal D at the rising edge of the signal inputted to the clock input terminal C, and outputs the taken data from the data output terminal Q as taken data. To do. Captured data DL0 to DL19 are output from data output terminals Q of flip-flops DF0 to DF19.

  The reset signal generated by the reset circuit 142 is input to the reset input terminals R of the flip-flops DF0 to DF19. The reset circuit 142 is a rise detection circuit, and outputs a pulse signal that changes to the L level in synchronization with the rise timing of the reception data D. Accordingly, the flip-flops DF0 to DF19 are initialized at the rising timing of the reception data D.

  FIG. 7 shows a circuit diagram of a configuration example of the pulse width detection circuit 150 of FIG. 7, parts that are the same as those in FIG. 3 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

The pulse width detection circuit 150 in FIG. 7 detects an error based on the captured data DL0 and DL17 and outputs an error detection result signal ERR. Captured data DL0 and DL17 represent states before and after captured data DL1 to DL16 corresponding to data obtained by pulse width modulation of 4-bit display data. The error detection result signal ERR changes to the H level when the display data “(0) ₁₆ ” (= (0000) ₂ ) has a pulse width smaller than the pulse width modulated data, based on the captured data DL0. . Further, the error detection result signal ERR is set to the H level when the display data “(F) ₁₆ ” (= (1111) ₂ ) has a pulse width larger than the pulse width modulated data based on the captured data DL17. Change.

  In addition, the pulse width detection circuit 150 includes an upper bit decoder 152. The pulse width detection circuit 150 performs an exclusive OR operation in the order of the acquisition data DL1, DL2, DL3,..., DL16 of the acquisition data DL1 to DL16, thereby obtaining the least significant bit RD of the 4-bit reception data. <0> is generated. Further, the upper bit decoder 152 generates each bit of the upper bits RD <3: 1> of the received data of 4 bits by decoding the fetched data DL2 to DL16. The reception data RD <3: 0> detected by the pulse width detection circuit 150 in this way is supplied to the drive circuit 32 of the display driver 30.

  FIG. 8 shows an example of a simulation result of the data receiving circuit 100 according to the first embodiment. FIG. 8 shows the received data D, the captured data DL0 to DL19, the detected received data RD <3> to RD <0>, and the error detection result signal ERR, with the time axis on the horizontal axis. In FIG. 8, in order to explain operations peculiar to the first embodiment, the pulse width of the reception data D is increased by 0.5 ns for each cycle, and the acquisition data DL0 to DL19 and the reception data RD are increased. <3> to RD <0> and changes in the error detection result signal ERR.

  Unlike FIG. 2, when the positions of the falling edges are uniformly defined, the reception data detected by the pulse width detection circuit 150 is increased when the pulse width of the reception data D is increased by a predetermined length every cycle. The value of RD <3: 0> increases at a certain rate.

  On the other hand, in the first embodiment, the step size is reduced as it is closer to the reference timing, and the step size is increased as it is farther from the reference timing. Accordingly, when the pulse width of the reception data D is increased by a predetermined length for each cycle, the value of the reception data RD <3: 0> detected by the pulse width detection circuit 150 is the case where the pulse width is small. When the pulse width is large compared to the above, it is difficult to increase.

  FIG. 9 shows another example of the simulation result of the data receiving circuit 100 according to the first embodiment. FIG. 9 shows the reception data D, the acquisition clocks CL0 to CL19, and the detected reception data RD <3> to RD <0> with the time axis on the horizontal axis. 9 is the same time axis as FIG. 8, and similarly to FIG. 8, the pulse width of the reception data D is increased by 0.5 ns for each cycle, the acquisition clocks CL0 to CL19, and the reception data It represents changes in RD <3> to RD <0>.

  As described with reference to FIG. 8, when the falling edge positions are uniformly defined, if the pulse width of the reception data D is increased by a predetermined length every cycle, the acquisition clocks CL0 to CL19 are It changes to H level at a constant rate. By doing so, the plurality of flip-flops constituting the data capture circuit 140 can capture the H level data when the corresponding capture clock changes to the H level.

  On the other hand, in the first embodiment, the step size is reduced as it is closer to the reference timing, and the step size is increased as it is farther from the reference timing. Therefore, when the pulse width of the reception data D is increased by a predetermined length every cycle, the acquisition clocks CL0 to CL19 do not change to the H level at a constant rate. As shown in FIG. 9, among a plurality of flip-flops constituting data fetch circuit 140, a flip-flop to which a fetch clock that cannot sufficiently rise to H level is input cannot fetch H level data. . As a result, when the pulse width is larger than when the pulse width is small, the value of the reception data RD <3: 0> detected by the pulse width detection circuit 150 is difficult to increase.

  As described above, in the first embodiment, display data is received by pulse width modulation in which the position of each falling edge is defined so that the step size becomes coarser as the distance from the reference timing increases. Thereby, the position of the falling edge close to the reference timing can be accurately defined. On the other hand, the position of the falling edge far from the reference timing has a large step size, so that the position of the falling edge can be accurately defined even if there is element variation.

  As a result, the reference timing extracted from the received data can be sequentially delayed to generate the capture timing of each falling edge, so that the position of the falling edge can be accurately defined without providing a PLL circuit. be able to. As a result, it is possible to increase the number of bits of pulse width modulation, and to transmit and receive large-capacity display data at high speed at low cost even at a frequency exceeding the measurement limit of the measuring device.

[Second Embodiment]
In the first embodiment, the optimum delay values of the delay circuit 110, the output buffer 120, the plurality of delay circuits DC0 to DC19, the clock buffers CB0 to CB19, and the termination circuit 132 are determined by the display data supply device 20 or the like. Explained as what to do. However, the embodiment according to the present invention is not limited to this.

  FIG. 10 is a block diagram showing a configuration example of the data receiving circuit according to the second embodiment of the present invention. 10 shows a configuration example in the case of receiving reception data in which 4-bit display data is modulated by pulse width modulation, as in FIG. 10, parts that are the same as those in FIG. 3 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

  The data receiving circuit 100a in the second embodiment includes a delay circuit 110, an output buffer 120, a capture timing generation circuit 130, a data capture circuit 140, a pulse width detection circuit 150, a delay control register 160, A delay control circuit 180a. The data receiving circuit 100a includes a timing adjustment control register 190 and a timing adjustment control circuit 200. The main difference between the configuration of the data receiving circuit 100 shown in FIG. 3 and the configuration of the data receiving circuit 100a in the second embodiment is that a timing adjustment control register 190 and a timing adjustment control circuit 200 are added. Such a data receiving circuit 100a can be provided in place of the data receiving circuit 100 in the display driver 30 of FIG. Of the circuits constituting the data receiving circuit 100a, circuits similar to those in FIG. 3 can be configured in the same manner as those shown in FIG. 6 or FIG.

  A control value for performing timing adjustment control is set in the timing adjustment control register 190 by the display data supply device 20 or the like.

  FIG. 11 shows an outline of the configuration of the timing adjustment control register 190. The timing adjustment control register 190 is a register configured to be accessible by the display data supply device 20 or the like.

  The timing adjustment control register 190 includes an output data register 192, a timing adjustment forced enable register 194, and a timing adjustment enable register 196.

In the output data register 192, the value of data transmitted from the display data supply device 20 to the data receiving circuit 100a is set by the display data supply device 20 or the like. When “(0) ₁₆ ” is set in the output data register 192, the data receiving circuit 100a receives data obtained by pulse-width-modulating 4-bit data corresponding to the “(0) ₁₆ ” value. When “(F) ₁₆ ” is set in the output data register 192, data obtained by pulse width modulation of 4-bit data corresponding to the “(F) ₁₆ ” value is received by the data receiving circuit 100 a.

  In the timing adjustment forced enable register 194, an enable bit for instructing to forcibly perform timing adjustment control is set by the display data supply device 20 or the like. When the enable bit is set in the timing adjustment forced enable register 194, the data receiving circuit 100a forcibly performs control for adjusting the delay value for defining the timing of taking in the value set in the output data register 192. .

  In the timing adjustment enable register 196, an enable bit for instructing to perform timing adjustment control by the display data supply device 20 or the like is set. When the enable bit is set in the timing adjustment enable register 196, the data reception circuit 100a adjusts the delay value for defining the timing of taking in the value set in the output data register 192, for example, during the blanking period. Take control.

  When the enable bit is set in the timing adjustment forced enable register 194 or the timing adjustment enable register 196 by the display data supply device 20 or the like, the data reception circuit 100a performs the following timing adjustment control. As a result of the timing adjustment control, an optimum control value is set in the delay control register 160.

  12 and 13 are flowcharts showing an operation example of the timing adjustment control in the second embodiment. FIG. 13 shows a flowchart of an operation example performed in step S11 of FIG. The flow shown in FIGS. 12 and 13 is desirably performed in step S1 as the delay adjustment step in FIG.

  First, the data receiving circuit 100a determines whether or not there is a forced calibration instruction in the timing adjustment control circuit 200 (step S10). Specifically, in step S10, the timing adjustment control circuit 200 determines whether or not an enable bit is set in the timing adjustment forced enable register 194. When the enable bit is set in the timing adjustment forced enable register 194 (step S10: Y), the timing adjustment control circuit 200 performs timing adjustment control (step S11), and ends a series of processing (end).

  When the enable bit is not set in the timing adjustment forced enable register 194 (step S10: N), the timing adjustment control circuit 200 determines whether or not there is a timing calibration instruction (step S12). Specifically, in step S12, the timing adjustment control circuit 200 determines whether an enable bit is set in the timing adjustment enable register 196. When the enable bit is set in the timing adjustment enable register 196 (step S12: Y), the timing adjustment control circuit 200 performs timing adjustment control during the blanking period. That is, the timing adjustment control circuit 200 waits until the vertical synchronization signal VSYNC becomes active (step S13: N). When the vertical synchronization signal VSYNC becomes active (step S13: Y), the timing adjustment control circuit 200 waits until the horizontal synchronization signal HSYNC for a predetermined number of lines becomes active (step S14: N). When the horizontal synchronization signals HSYNC for a predetermined number of lines become active (step S14: Y), the timing adjustment control circuit 200 performs timing adjustment control (step S11), and ends a series of processing (end).

In step S11, as shown in FIG. 13, the timing adjustment control circuit 200 determines whether or not the value set in the output data register 192 is “(0) ₁₆ ” (step S20). When “(0) ₁₆ ” is set in the output data register 192 (step S20: Y), the timing adjustment control circuit 200 waits for a predetermined period (step S21). Within this predetermined period, data with the shortest pulse width is transmitted from the display data supply device 20, and the received data is detected by the pulse width detection circuit 150 of the data reception circuit 100a.

  Subsequent to step S21, the timing adjustment control circuit 200 determines the presence or absence of an error based on the error detection result signal ERR from the pulse width detection circuit 150 (step S22). When it is determined that there is no error based on the error detection result signal ERR (step S22: Y), the timing adjustment control circuit 200 determines whether the pulse width is “0” based on the reception data RD <3: 0>. It is determined whether or not (step S23). When the pulse width is “0” (step S23: Y), the timing adjustment control circuit 200 sets a control value corresponding to the current delay value in the delay circuit control register 162 (step S24), and a series of processes End (end).

  When it is determined in step S22 that there is an error based on the error detection result signal ERR (step S22: N), the timing adjustment control circuit 200 increases the control value set in the delay circuit control register 162 (step S22). S25), the process returns to step S21.

  When the pulse width is not “0” in step S23 (step S23: N), the timing adjustment control circuit 200 decreases the control value set in the delay circuit control register 162 (step S26), and returns to step S21.

When “(0) ₁₆ ” is not set in the output data register 192 (step S20: N), the timing adjustment control circuit 200 determines whether the value set in the output data register 192 is “(F) ₁₆ ”. It is determined whether or not (step S27).

When “(F) ₁₆ ” is set in the output data register 192 (step S27: Y), the timing adjustment control circuit 200 waits for a predetermined period (step S28). Within this predetermined period, data having the longest pulse width is transmitted from the display data supply device 20, and the received data is detected by the pulse width detection circuit 150 of the data reception circuit 100a.

  Subsequent to step S28, the timing adjustment control circuit 200 determines the presence or absence of an error based on the error detection result signal ERR from the pulse width detection circuit 150 (step S29). When it is determined that there is no error based on the error detection result signal ERR (step S29: Y), the timing adjustment control circuit 200 determines whether the pulse width is “15” based on the reception data RD <3: 0>. It is determined whether or not (step S30). When the pulse width is “15” (step S30: Y), the timing adjustment control circuit 200 sets the control value corresponding to the current delay value to the output buffer control register 164, the capacitance value control register 166, and the clock buffer. The control register 168 and the termination circuit control register 170 are set (step S31), and the series of processing ends (end).

  When it is determined in step S29 that there is an error based on the error detection result signal ERR (step S29: N), the timing adjustment control circuit 200 outputs the output buffer control register 164, the capacitance value control register 166, and the clock buffer control. The control value set in either the register 168 or the termination circuit control register 170 is increased (step S32), and the process returns to step S28.

  When the pulse width is not “15” in step S30 (step S30: N), the timing adjustment control circuit 200 outputs the output buffer control register 164, the capacitance value control register 166, the clock buffer control register 168, and the termination circuit control register. The control value set to any one of 170 is decreased (step S33), and the process returns to step S28.

When “(F) ₁₆ ” is not set in the output data register 192 (step S27: N), the timing adjustment control circuit 200 ends a series of processing (end).

As described above, in the second embodiment, the first data obtained by performing the pulse width modulation on “(0) ₁₆ ” in which the pulse width of the reception data is the shortest and the pulse width of the reception data in the longest “(F) ₁₆ ”is used to adjust the delay value of the delay means of the data receiving circuit 100 a using the second data obtained by pulse width modulation. Here, the delay means of the data receiving circuit 100a includes at least one of a delay circuit 110, an output buffer 120, delay circuits DC0 to DC19, clock buffers CB0 to CB19, and a termination circuit 132.

  Thus, for example, the end timing of the H level fixed period t0 can be defined by adjusting the delay value based on the reception data with the shortest pulse width. Further, the lower timing of the L level fixed period t1 can be defined by adjusting the delay value based on the reception data having the shortest pulse width. As a result, the 15 step sizes are automatically defined within the period excluding the H level fixed period t0 and the L level fixed period t1 within one cycle period.

  As described above, according to the second embodiment, the delay circuit 110, the output buffer 120, the delay circuits DC0 to DC19, the clock buffers CB0 to CB19, and the termination circuit 132 are forcibly or during a predetermined period. The control value can be determined. As a result, an optimum control value is always set even during operation, and multi-bit pulse width modulated data can be received stably. Therefore, even at a frequency exceeding the measurement limit of the measuring device, a large amount of display data can be transmitted / received at high speed at a low cost.

[Modification]
In the first embodiment or the second embodiment, the configuration of the delay circuit 110 has been described by taking, for example, the configuration shown in FIG. 6 as an example, but the embodiment according to the present invention is not limited to this.

  FIG. 14 shows a configuration example of the delay circuit in the modification of the first embodiment or the second embodiment.

  The delay circuit 110 in the present modification includes a plurality of first delay elements DS1, a plurality of second delay elements DS2, and an output selection unit SEL. The plurality of first delay elements DS1 are connected in cascade, and the reception data D from the display data supply device 20 is input to the input of the first delay element DS1 in the first stage, and each first delay element DS1. Are connected to the output selector SEL. The output of each first delay element DS1 is also connected to the output selection unit SEL via each second delay element DS2.

  The second delay element DS2 is connected to the high-potential side power supply via any one of a plurality of resistance elements having different resistance values, and can adjust the delay time of the rise of the output signal. ing. The second delay element DS2 is connected to the low-potential-side power supply via any one of a plurality of resistance elements having different resistance values, and can adjust the delay time of the fall of the output signal. It is like that.

  The delay control circuit 180 outputs a control signal C1 corresponding to the control value set in the delay circuit control register 162 to the plurality of second delay elements DS2 and the output selection unit SEL. Each second delay element DS2 is connected to a high potential power source and a low potential power source via a resistance element selected based on the control signal C1. The output selection unit SEL selects any one of the outputs of the plurality of first delay elements DS1 and the plurality of second delay elements DS2 based on the control signal C1, and passes through the selected path. The signal is output to the output buffer 120 as an output signal.

  According to the delay circuit 110 in this modification, the delay value can be finely adjusted with higher accuracy than the delay circuit having the configuration shown in FIG.

[Others]
FIG. 15 is an explanatory diagram of display data supplied from the display data supply device 20 of FIG. 1 to the display driver 30. The display data is composed of 12 bits D11 to D0. D11 is the upper bit side and D0 is the lower bit side.

  When transmitting such display data to the display driver 30, the display data supply device 20 divides the display data into four bits and performs pulse width modulation on the divided data.

  Here, with respect to display data, the upper bit side contributes more greatly to the change in luminance than the lower bit side. Therefore, as shown in FIG. 15, the first group is D11, D8, D5, D2, the second group is D10, D7, D4, D1, the third group is D9, D6, D3, D0, The upper bits of the group are D11, D10, and D9. Therefore, when 4-bit data of each group is subjected to pulse width modulation, even if a bit error occurs due to noise or the like near the falling edge of the pulse, the lower bits are not detected, and the pulse width corresponding to the upper bits has a high probability. Can be detected. Therefore, even when the display panel 40 is driven using such data, the influence on the display image is small.

〔Electronics〕
The display driver provided with the data receiving circuit in any of the above embodiments or the modifications thereof can be applied to, for example, the following electronic apparatus.

  FIGS. 16A and 16B are perspective views illustrating the configuration of an electronic device having a display driver including a data receiving circuit according to any of the above-described embodiments or modifications thereof. FIG. 16A illustrates a perspective view of a configuration of a mobile personal computer. FIG. 16B illustrates a perspective view of a structure of a mobile phone.

  A personal computer 500 illustrated in FIG. 16A includes a main body portion 510 and a display portion 520. The display unit 520 includes a display driver including the data receiving circuit in any one of the above-described embodiments or modifications thereof. The main body 510 is provided with a keyboard 530. Operation information via the keyboard 530 is analyzed by a control unit (not shown), and an image is displayed on the display unit 520 in accordance with the operation information. Since the display portion 520 can transmit and receive signals at high speed, it is possible to provide the personal computer 500 capable of displaying very high definition at a low cost.

  A cellular phone 600 illustrated in FIG. 16B includes a main body portion 610 and a display portion 620. The display unit 620 includes a display driver including the data receiving circuit in any one of the above-described embodiments or modifications thereof. The main body 610 is provided with a key 630. Operation information via the key 630 is analyzed by a control unit (not shown), and an image is displayed on the display unit 620 according to the operation information. Since the display portion 620 can transmit and receive signals at high speed, it is possible to provide the mobile phone 600 capable of displaying very high definition at low cost.

  It should be noted that the electronic device on which the display driver including the data receiving circuit in any of the above-described embodiments or modifications thereof is mounted is not limited to those shown in FIGS. Absent. For example, personal digital assistants (PDAs), digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic paper, calculators, word processors, workstations, video phones, POS (Point of sale systems ) Devices such as terminals, printers, scanners, copiers, video players and touch panels. According to any one of the above-described embodiments or modifications thereof, the above-described electronic device can contribute to realization of a large capacity and high-speed processing by accurately receiving a high-speed signal.

  As described above, the data receiving circuit, the electronic device, the data receiving method, and the like according to the present invention have been described based on any one of the above-described embodiments or modifications thereof. It is not limited to examples. For example, the present invention can be implemented in various modes without departing from the gist thereof, and the following modifications are possible.

  (1) In any of the above-described embodiments or modifications thereof, an example in which the data receiving circuit according to the present invention is mounted on a display driver has been described, but the present invention is not limited to this. That is, it goes without saying that the data receiving circuit according to the present invention can be applied to a circuit not related to display.

  (2) In any of the above-described embodiments or modifications thereof, the data receiving circuit has been described as outputting captured data DL0 to DL19, but the present invention is not limited to this. For example, the data receiving circuit may have a configuration for outputting the captured data DL0 to DL17. Further, when the error detection result signal ERR is not output, the data receiving circuit may have a configuration for outputting the fetched data DL1 to DL16.

  (3) In any of the above-described embodiments or modifications thereof, it has been described that pulse width modulation is mainly performed on 4-bit display data. However, the present invention is not limited to this. For example, the present invention can be applied to a device that performs pulse width modulation on display data of a plurality of bits other than 4 bits.

  (4) In any of the above-described embodiments or modifications thereof, an example of pulse width modulation in which the rising edge of received data is used as the reference timing and the position of the falling edge is modulated in order to detect the H level width will be described. However, the present invention is not limited to this. For example, the present invention can also be applied to the detection of the L level width. In this case, since the position of the falling edge of the reception data is modulated, as the plurality of capture timings, the step size is increased as the capture timing is closer to the reference timing. Then, the width of the L level may be detected based on the rising edge of the received data that is the end timing of the L level fixed period shown in FIG.

  (5) In the second embodiment, the example in which the timing adjustment control is performed during the blanking period when the enable bit is set in the timing adjustment enable register 196 has been described. However, the present invention is limited to this. is not.

  (6) In any of the above-described embodiments or modifications thereof, the present invention has been described as a data receiving circuit, an electronic device, a data receiving method, and the like, but the present invention is not limited to this. For example, a program in which the processing procedure of the data receiving method according to the present invention is described, and a recording medium on which the program is recorded may be used.

DESCRIPTION OF SYMBOLS 10 ... Electronic device, 20 ... Display data supply apparatus, 22 ... Display data generation circuit,
24 ... Data transmission circuit, 26 ... PLL circuit, 28 ... Transmission control unit,
30 ... Display driver, 32 ... Drive circuit, 40 ... Display panel,
100, 100a ... data receiving circuit, 110 ... delay circuit (data delay unit)
DESCRIPTION OF SYMBOLS 120 ... Output buffer, 130 ... Capture timing generation circuit (capture timing generation part), 132 ... Termination circuit, 134 ... Capacity initialization circuit
140: Data acquisition circuit (data acquisition unit), 142: Reset circuit,
150: Pulse width detection circuit (reception data detection unit), 152 ... Upper bit decoder,
160 ... delay control register,
162 ... delay circuit control register (first delay setting register),
164 ... Output buffer control register (second delay setting register),
166: Capacitance value control register (third delay setting register),
168: Clock buffer control register (fourth delay setting register),
170: Termination circuit control register (fifth delay setting register),
180, 180a ... delay control circuit, 190 ... timing adjustment control register,
192 ... Output data register, 194 ... Timing adjustment forced enable register,
196: Timing adjustment enable register, 200: Timing adjustment control circuit,
C1 to C5 ... control signal, CB0 to CB19 ... clock buffer,
CL0 to CL19 ... Capture clock, D, RD ... Receive data,
DC0 to DC19 ... delay circuit, DF0 to DF19 ... flip-flop,
DL0 to DL19 ... captured data, DS1 ... first delay element,
DS2 ... second delay element, ERR ... error detection result signal, t0 ... H level fixed period,
t1 ... L level fixed period, tw _{0 to} tw ₁₅ ... step size, SEL ... output selection unit

Claims (16)

A data receiving circuit that receives a plurality of bits represented by a pulse width from a reference timing, the pulse width being modulated by pulse width modulation having two or more step sizes,
An acquisition timing generation unit that sequentially delays the data to generate a plurality of acquisition timings having two or more types of step sizes;
A data capture unit that captures predetermined data at the multiple capture timings generated by the capture timing generation unit;
A data receiving circuit, comprising: a received data detecting unit that detects received data based on fetched data fetched at each fetch timing in the data fetching unit. In claim 1,
The plurality of capture timings are:
A data receiving circuit characterized in that the step size becomes smaller as the acquisition timing is closer to the reference timing. In claim 1,
The plurality of capture timings are:
The data receiving circuit, wherein the step size becomes larger as the acquisition timing is closer to the reference timing. In any one of Claims 1 thru | or 3,
The data fetching unit
A plurality of flip-flops provided corresponding to each of the plurality of capture timings and initialized prior to reception of the data;
Each of the plurality of flip-flops is
A data receiving circuit that captures a capture clock that changes at a corresponding capture timing. In any one of Claims 1 thru | or 4,
A data delay unit for delaying the data;
A first delay setting register in which a control value corresponding to a power supply voltage of the data delay unit is set;
A data receiving circuit, wherein a power supply voltage of the data delay unit is set to a voltage corresponding to the control value set in the first delay setting register. In claim 5,
An output buffer provided between the data delay unit and the capture timing generation unit, buffering the output of the data delay unit and then outputting to the capture timing generation unit;
A second delay setting register in which a control value corresponding to the power supply voltage of the output buffer is set;
A data receiving circuit, wherein a power supply voltage of the output buffer is set to a voltage corresponding to the control value set in the second delay setting register. In any one of Claims 1 thru | or 6.
The capture timing generation unit
A data receiving circuit having a configuration in which a plurality of delay circuits each composed of a resistive element and a capacitive element are connected in cascade, and outputs an output of each delay circuit as each capture timing. In claim 7,
A plurality of clock buffers each connected to an output of a corresponding delay circuit;
A third delay setting register in which a control value corresponding to a power supply voltage of the plurality of clock buffers is set;
A data receiving circuit, wherein power supply voltages of the plurality of clock buffers are set to voltages corresponding to the control values set in the third delay setting register. In claim 7 or 8,
A termination circuit connected to terminations of the plurality of delay circuits;
A fourth delay setting register in which a control value corresponding to the capacitance value of the termination circuit is set;
A data receiving circuit, wherein a capacitance value of the termination circuit is set to a capacitance value corresponding to the control value set in the fourth delay setting register. In any one of Claims 7 thru | or 9,
A fifth delay setting register in which a control value corresponding to the capacitance value of the capacitive element constituting the delay circuit is set;
A data receiving circuit, wherein a capacitance value of the capacitive element is set to a capacitance value corresponding to the control value set in the fifth delay setting register. In any of claims 7 to 10,
A data receiving circuit comprising: a capacitor initializing circuit for initializing charges charged in a capacitor element constituting each of the plurality of delay circuits prior to output of a corresponding capture timing.   An electronic apparatus comprising the data receiving circuit according to claim 1. A data reception method for receiving data modulated by pulse width modulation in which a plurality of bits are represented by a pulse width from a reference timing, and the pulse width has two or more step sizes,
An acquisition timing generation step for sequentially delaying the reference timing corresponding to the data change timing to generate a plurality of acquisition timings having two or more types of step sizes; and a data acquisition for acquiring the plurality of acquisition timings. Included steps,
A data reception method comprising: a reception data detection step of detecting reception data based on the acquisition data acquired at the plurality of acquisition timings in the data acquisition step. In claim 13,
The plurality of capture timings are:
A data receiving method, wherein the step size becomes smaller as the acquisition timing is closer to the reference timing. In claim 13 or 14,
A delay adjustment step of adjusting at least one of a power supply voltage of a delay unit that delays the reference timing and a capacitance value of a capacitive element that constitutes the delay unit;
The capture timing generation step includes:
The data receiving method, wherein the reference timing is sequentially delayed by the delay means adjusted in the delay adjustment step to generate the plurality of capture timings. In claim 15,
The delay adjustment step includes:
A data receiving method for adjusting a delay value of the delay means, using first data having the shortest pulse width of the data and second data having the longest pulse width of the data. .

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