JPH01314451A - Phase jitter detecting circuit - Google Patents

Abstract

PURPOSE:To detect a phase jitter without using a software by holding the peak of a sawtooth-shaped wave, which is generated from the level change time of a clock signal just after the level of a digital data signal is changed to the next level change time, and discriminating the presence and absence of the phase jitter. CONSTITUTION:The digital data signal is converted to a pulse, which rises with synchronizing to the rising of the clock signal just after rising and falls with synchronizing to the falling of the digital data signal and a clock signal CLK. A capacitor 44 is discharged with synchronizing to the rising of a pulse A and a current driving circuit is driven by a differentiating pulse C at the rising time of the clock signal CLK. Then, the sawtooth-shaped wave is outputted from a sawtooth-shaped wave generating circuit 1. The peak of the sawtooth-shaped wave is held by a peak hold circuit 7 and the presence and absence of the jitter is discriminated by a discriminating circuit 8.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a phase jitter detection circuit.

[Prior Art] In digital signal transmission, it is desirable that the signal state at clock timing be stable at 1 or 0.

However, when the pulse width of the digital signal fluctuates due to external or internal factors, the state at the clock timing coincides with the state transition of the signal, resulting in erroneous identification. As a method for solving this problem, a method is known in which coding is performed to check for errors and errors are detected using software.

' [Problem to be solved by the invention] Since the conventional phase jitter detection circuit is configured as described above, the following (1)
, there were problems such as (2).

(1) Function for error detection in signal encoding (
It is necessary to provide a large degree of signal redundancy in order to retain information (information).

(2) Signal errors themselves are difficult to detect at a lower level such as a transmitter/receiver, and processing at a higher level is required, making the configuration complicated.

An object of the present invention is to solve the above-mentioned problems and provide a phase jitter detection circuit that does not use software and has an Ml-configuration.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a clock signal from the time when the level of the clock signal changes immediately after the level of the digital data signal changes to the time when the level of the digital data signal changes immediately after the level of the digital data signal changes. Until the data signal level changes,
The present invention includes a sawtooth wave generating means for generating a sawtooth wave, a peak holding means for holding the peak of the sawtooth wave, and a determining means for determining the presence or absence of phase jitter from the peak of the held sawtooth wave. Features.

[Function] In the present invention, the sawtooth wave is generated from the time when the level of the clock signal changes immediately after the level of the digital data signal changes until the time when the level of the digital data signal changes immediately after the level change of the digital data signal. The generation means generates a sawtooth wave, the peak of the generated sawtooth wave is held by the peak hold means, and the presence or absence of jitter is determined by the determination means from the peak of the held sawtooth wave.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the invention.

In the figure, 1 is a sawtooth wave generating circuit, and as shown in FIG. 2, a latch circuit 2 that latches received data DATA,
It is comprised of a differentiator 3 and a circuit 4 that differentiate the clock signal CL. Table 1 shows an example of the truth values of the received data DATA input to the latch circuit 2 and the clock signal CL.

Table 1 shows a specific example of circuit 4, which is composed of an integrator 5 that integrates the output of the latch circuit 2, a current drive circuit 6 driven by the differentiator 3, and a circuit that resets the integrator output signal. In FIG. 3, 41 is a delay circuit, 42 is a buffer IC, 43 is an NPN transistor, 44 is a capacitor, 45 is an NPN transistor, 48 is a buffer IC, and 47 is a current source.

Reference numeral 7 denotes a peak hold circuit, which serves as a holding means to hold the peak of the sawtooth wave output from the sawtooth wave generation circuit 1. Reference numeral 8 denotes a discrimination circuit, which serves as a discrimination means to discriminate the presence or absence of phase jitter from the peak of the sawtooth wave held by the peak hold circuit 7.

An example of the output signal of the sawtooth wave generation circuit 1 and the output signal of the discrimination circuit 8 is shown in FIG.

Next, the operation will be explained.

(1) If there is no jitter in the digital data signal, the fifth
The digital data signal [IATA1] shown in Figure (a) is
The latch circuit 2 causes the pulse A shown in FIG. 5(c) to rise in synchronization with the rise of the clock signal immediately after the rise of the digital data signal, and to synchronize with the fall of the digital data signal and clock signal CL. It is converted into a falling pulse.

The capacitor 44 is discharged in synchronization with the rise of this pulse A, and the current drive circuit 6 is driven by the differential pulse C at the rise of the clock signal CL.
A sawtooth wave as shown in FIG. 5(d) is produced by the sawtooth generation circuit 1.
is output from.

Then, when the peak of the sawtooth wave is held by the peak hold circuit 7, the held peak becomes VP
Since there are only II and vPL, the determination circuit 8 determines that there is no jitter.

(2) When the digital data signal has jitter In this case, if the digital data signal becomes as shown in FIG. 6(a), the pulse output from the latch circuit 2 will be as shown in FIG. 6(C). It becomes like this. Therefore, in the sawtooth wave output from the sawtooth wave generation circuit 1, the peak of the jittered portion is larger than VPL and smaller than Vpu, as shown in FIG. 6(d).

Then, when the peak of the sawtooth wave is held by the peak hold circuit 7, the held peak value is vP
□r vP In addition to L, the value is smaller than VPH and larger than VPL, so the discrimination circuit 8 determines that there is jitter.

[Effects of the Invention] As explained above, according to the present invention, from the time when the level of the clock signal changes immediately after the level of the digital data signal changes, the level change of the digital data signal immediately after the level change of the digital data signal changes. Since the peak of the sawtooth wave generated up to the time is held and the presence or absence of phase jitter is determined from the held peak, a phase jitter detection circuit that does not require software and has a simple configuration can be created. It has the effect of being able to provide

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, and Fig. 2 is a block diagram showing an embodiment of the present invention.
3 is a circuit diagram showing a specific example of the circuit 4 shown in FIG. 2. FIG. 4 is a diagram showing the output signal of the sawtooth wave generation circuit 1 and a discrimination circuit. Figure 5 is a waveform diagram showing an example of the output signal of No. 8. Figure 5 is a diagram showing the waveforms of each part in Figure 1 when there is no jitter. Figure 6 is a diagram showing the waveforms of various parts in Figure 1 when there is jitter. It is. 1... Sawtooth wave generation circuit, 7... Peak hold circuit, 8... Discrimination circuit. Patent applicant: Sumitomo Electric Industries, Ltd.

Claims (1)

[Claims] 1) A sawtooth waveform is generated from the time when the level of the clock signal changes immediately after the level of the digital data signal changes until the time when the level of the digital data signal changes immediately after the level change of the digital data signal. The present invention is characterized by comprising: sawtooth wave generating means for generating the sawtooth wave; peak holding means for holding the peak of the sawtooth wave; and determining means for determining the presence or absence of phase jitter from the peak of the held sawtooth wave. phase jitter detection circuit. 2) The sawtooth wave generating means linearly rises in synchronization with the rise of the clock signal immediately after the rise of the digital data signal, and then until it falls in synchronization with the fall of the digital data signal immediately after the rise. 2. The phase jitter detection circuit according to claim 1, wherein the circuit generates a sawtooth wave that falls and starts rising linearly every time the clock signal rises. 3) The sawtooth wave generating means linearly rises in synchronization with the fall of the clock signal immediately after the digital data signal falls, and then falls in synchronization with the rise immediately after the fall of the digital data signal. 2. The phase jitter detection circuit according to claim 1, wherein the clock signal falls every time the clock signal falls and starts rising linearly until the clock signal falls.