JPH0420297B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal transmission method for serially transmitting digital signals such as PCM audio signals.

In recent years, analog signals such as audio signals have been processed using PCM (Pulse Code Modulation).
It is becoming more and more common for digital signals to be converted into digital signals and transmitted, recorded, and reproduced via signal transmission media or recording media. In such digital audio signals, etc., one sample data is multi-bit data obtained by quantizing and encoding one sample value of the original analog signal, and one word of the digital signal is constructed based on this one sample data. There is. In addition to the above one sample data, one word contains various data bits such as error prevention data bits, data validity determination bits, user bits, channel status information bits, parity bits, etc., as necessary. is included.

The following characteristics are required for a method of serially transmitting digital signals containing various types of data.

That is, first of all, in order to enable reliable transmission even when the transmission path includes AC coupling, and to ensure threshold detection in either electrical or optical systems, it is necessary to use a system that does not contain DC components. (DC-free) transmission waveform is required. Next, the transmitted waveform is required to be polarity-free;
This contributes to the simplification of the device without affecting the transmission signal even if one and the other of a pair (two) transmission lines such as a twisted pair are switched. Next, it is necessary that hardware implementation be simple and easy. Furthermore, it is necessary to satisfy the transmission distance when applied to broadcasting stations, studios, etc.

A so-called digital FM method is known as a digital signal modulation method that satisfies all of these requirements. This digital FM method is
A transition is always placed at the edge (or boundary) of each bit of binary data of “1” and “0”, and at the center position of each bit, the first value, for example, “1” is inverted. This is a modulation method in which there is no inversion when the second value is 0, for example, and is expressed as a signal waveform as shown in FIG. 1 corresponding to digital binary data. In this digital FM signal, when the data bit period is T, the interval from the above inversion to the next inversion is:
Since it is either T/2 or T, it is extremely easy to detect and maintain the bit clock signal.
Moreover, the above-mentioned DC-free and polarity-free conditions are also satisfied.

By the way, when transmitting a digital signal serially, that is, when all bits of each word are transmitted sequentially one bit at a time via a transmission line (or a pair), the beginning of each word (or within each word) (the predetermined location of) is required. The display part of the word start (or predetermined position) provided for each word is as follows:
This is a so-called word synchronization signal portion, and is required to be clearly distinguishable from other data portions within a word. Furthermore, it is necessary to reduce as much as possible the time fluctuations of the rising and falling edge portions of the signal, which are the reference timing determining portions of the word synchronization signal. In other words, since this edge section is supplied as reference phase information to the PLL circuit of the receiving side (or playback side) circuit, accuracy is required in an extremely short time unit compared to the bit period. .

Here, when transmitting and receiving digital signals, the rising waveform and falling waveform of the signal are not necessarily the same (completely symmetrical), and the difference between the on-operation time and off-operation time of the output switching element of the transmitting circuit is Errors in the rise time constant and fall constant due to differences in impedance corresponding to on/off operations of the signal transmission line, and time differences between on/off operations of switching elements in the receiving side circuit, etc. The timing of the edge portion of the word synchronization signal supplied to the PLL circuit in the section differs depending on whether it rises or falls. For this reason, although the polarity of the signal itself is arbitrary, for a series of serially transmitted digital signals, it is necessary that the word synchronization signal is unchanged in one of the polarities.

In view of such conventional circumstances, the present invention has been made to solve the above-mentioned problems.
It has a word synchronization signal that satisfies the polarity-free condition and can be clearly distinguished from other data in the word, and the polarity of the word synchronization signal does not change within a series of digital signals, and the word synchronization The object of the present invention is to provide a digital signal transmission method that requires a small number of bits in a signal part and simplifies the configuration of transmitting/receiving circuits (or the configuration of recording/reproducing circuits).

That is, the feature of the digital signal transmission method according to the present invention is that in the digital signal transmission method in which digital binary data consisting of a plurality of bits per word is digitally modulated and serially transmitted, each of the digital binary data is In addition to inverting at bit boundaries, a modulation rule is adopted in which the bit is inverted at the first value and not inverted at the second value at the center position of each bit, and each word is provided with a word synchronization signal and a parity bit. The word synchronization signal has a pulse width portion that is 1.5 times or more the bit period by providing a portion of the modulation rule that prohibits inversion at bit boundary positions, and the word synchronization signal has a pulse width portion that is 1.5 times or more the bit period, The parity data value is set so that the sum of the total number of bits that take the second value out of all the digital binary data including the word synchronization signal and parity data and the number of inversion prohibited portions is an even number. The polarity of the leading edge at the beginning of each word is fixed in the same direction.

Hereinafter, preferred embodiments of the present invention will be described.
This will be explained with reference to the drawings.

FIG. 2 shows an example of the word format of one word of a digital signal, and one word is composed of 32 bits. The first two bits of this one word are used as the word synchronization signal part S, which is the gist of the present invention, and the 24 bits D1 to D24 from the 3rd bit to the 26th bit are used as the 1st part of the audio signal, for example.
It is used for digital audio sample data that converts sample values into PCM. If necessary, the rear 4 in this sample data bits D1 to D24
Bits D21-D24 may be used as auxiliary data bits _X1 - _X4 . The next 27th and 28th bits are considered to be used, for example, as block/channel detection bits, and one block is made up of multiple temporally consecutive words (for example, 256 words), as shown in the block format shown in Figure 2. This is useful for determining the starting end position of a block when configuring a block, or for determining the starting end of each channel when dividing one block into a plurality of channels. Next, the 29th bit is the data validity determination bit V, the 30th bit is the user's bit U, and the 31st bit is the user's bit U.
The th bit is used as channel status data bit C, and the 32nd bit is used as a parity bit. In this case, user's bit U and channel status data bit C
Each block in the block format shown in FIG. 2 constitutes one word.

Next, the word synchronization signal, which is the gist of the present invention, will be explained with reference to FIG.

The signal waveforms A, B, and C in FIG. 3 indicate the first, second, and third embodiments, respectively, and indicate the edge position (3 By prohibiting transitions at two of the points (boundary positions), a word synchronization signal having a pulse width (distance between adjacent inversions) of 1.5 times or more the bit period T is obtained. For other edge positions, adjacent data and parity data are made continuous according to the rules of the digital FM method, and the above DC-free and polarity-free conditions are satisfied. ing. Regarding the parity data, if there are two locations where inversion is prohibited, the parity data is selected so that there is an even number of "0"s, including the 2-bit data of the word synchronization signal part, and the number of bits in one word is When is an even number of bits, such as the 32 bits in the example in Figure 2, even parity is used for all bits in one word (including word synchronization), and even parity is used for all bits in one word (including word synchronization), and even parity is used for all bits in one word (including word synchronization). odd parity if
is used. In this way, by setting the number of data "0"s in one word to an even number, the polarity of the leading edge at the start end of each word is fixed as either upward or downward. This is because, as is clear from the signal waveform in Figure 1, the polarity (direction) of the leading edge and trailing edge of the bit are equal when the data is "1", and are opposite when the data is "0". This is because the leading edge of the starting end of a word containing an even number of 0's and the trailing edge of the ending end (leading edge of the starting end of the next word) are reversed in the same direction. Furthermore, at this time, the polarity (orientation) of the trailing edge of the end of the word (the leading edge of the starting end of the next word) becomes opposite every time the number of inversion prohibited locations increases by one, and becomes the same at even numbered locations.

Here, in the digital signal waveform of FIG. 3A, which is the main part of the first embodiment of the present invention, the two bits S ₁ and S ₂ for the word synchronization signal are both set to "0", and the bit S ₁ At the leading edge of and the trailing edge of Bit S ₂ ,
Reversal of each is prohibited. In this case, if one word is 32 bits and the above bits S ₁ and S ₂ are also considered as data, in order to have an even number of "0"s, the data bits D ₁ to _{D 29} and the parity bit P must be 30 bits. The parity of the bits may be even, and even parity may be used as the parity bit P. For example, when a digital signal of "L" (low level) at bit _S1 and "H" (high level) at bit _S2 is received, the third
A word synchronization signal with the same polarity as in Figure A is obtained, and a rising waveform is always obtained at the boundary between bits _S1 and _S2 . Furthermore, since reversal is prohibited at the leading edge of bit _S1 and the trailing edge of bit _S2 ,
Non-inversion sections of 1.5T to 2T are obtained in the front and rear directions from the boundary position of bits S ₁ and S ₂ , respectively.

Next, in the digital signal waveform of FIG. 3B, which is the main part of the second embodiment of the present invention, bits S1 of the word synchronization signal part are set to " ₀ ", bit _S2 is set to "1", Boundaries of bits S ₁ , S ₂ , and bits
Reversal is prohibited at two locations on the trailing edge of _S2 . In this case, in order to make all 32 bits of one word an even number (“1” is also an even number), the bits must be
Since S ₂ is “1”, data bit D ₁ ~
It is necessary to use odd parity for the 30 bits of _D29 and parity bit P. That is, when the parity bit P is set for 30 bits of data and parity, odd parity is used, and even parity is used for all 32 bits of one word. In this second embodiment, between the leading edge of bit S ₁ and the center of bit S ₂
A non-reversal section of 1.5T is provided, and from the center of bit S ₂ to the rear, it is 1T (data D ₁ is "1")
Alternatively, a non-inversion section of 1.5T (data _D1 is "0") is provided. Of course, the polarity of the word synchronization signal remains unchanged.

Next, in the signal waveform of FIG. 3C, which is the main part of the third embodiment, bit S1 is set to " ₁ " and bit S2 is set to "_1" .
is set to “0”, and the front edge of bit _S1 and the bit
Reversal of S ₁ and S ₂ is prohibited at two points with the boundary.
In this case as well, as in the second embodiment, an odd parity may be used as the parity bit P for the 30 bits of data and parity.

Here, in the signal waveform diagrams of FIGS. 3A, B, and C, the solid line waveform and inversion position do not change, and the broken line waveform and inversion position change depending on the contents of data D ₁ to D ₂₉ (and parity P). Change. Further, the position of the symbol in each waveform diagram indicates the above-mentioned inversion prohibited position. Furthermore, EP and OP written at the position of each parity bit P indicate even parity and odd parity, respectively, and the numbers in parentheses indicate the parity when bits S ₁ and S ₂ of the word synchronization signal part are also considered as data. There is. In addition, these figures A, B, C
"H" and "L" of the word synchronization signal waveform can be inverted, and a pair of transmitter/receiver (or recording/reproducing device)
It is important that the polarity of the word synchronization signal remains unchanged within the serial digital signal that is transmitted and received continuously over time. Furthermore, the position of the parity bit P is not limited to the illustrated example, and may be located midway between the data bits _D1 to _D29 .

These three examples are all DC-free,
polarity-free, no change in the polarity of the word sync signal;
The distance between adjacent inversions of word sync signal is 1.5T
In addition to satisfying each of the above conditions, the word synchronization signal portion only requires 2 bits, and except for the prohibition of inversion at two locations, all the rules for modulation in the digital FM system are satisfied.

Therefore, the digital data signal can be easily modulated and demodulated, the circuit configuration is simple, and the polarity of the word synchronization signal does not change, so that the reference phase determining edge section (arrows A, B, and C in Figure 3) This has the advantage that the timing accuracy of the inversion section (shown in Figure 1) is high.

By the way, among the three embodiments in which the main parts are the word synchronization signals shown in FIGS. 3A, B, and C, the first example shown in FIG.
In the example, since the non-reversal section can be 2T,
FM deviation becomes deeper. Also, Figure 3C
In the third embodiment, when two consecutive 1.5T non-inversion sections appear when detecting a word synchronization signal on the receiving side, it is necessary to adopt the second 1.5T. , the circuit configuration becomes complicated and a delay time of at least 1.5T is required to detect the word synchronization signal. On the other hand, in the case of the second embodiment shown in FIG. 3B, the FM deviation is shallow, and the word synchronization signal can be detected in the first non-inversion section of 1.5T, and the next non-inversion section can be detected. Since it is sufficient to configure the circuit so that 1.5T is not adopted even if it appears, the circuit configuration is simple and the word synchronization signal can be detected immediately.

Next, FIG. 4 shows an example of a transmitting side (or recording side) circuit configuration of the digital signal transmission method according to the present invention, and shows an example using the word synchronization signal waveform of FIG. 3B, for example.

In FIG. 4, a timing generator 1 generates various timing pulses for circuit operation, and converts a load pulse with a word period and a bit clock with a bit period T shown in FIG. 5 into a parallel-serial conversion means. Sending to register 2. The shift register 2 has 32 parallel input terminals (load terminals) L ₁ to L ₃₂ corresponding to 32 bits per word, and in order from the input terminal L ₁ , bits S ₂ , S ₁ , and parity bits for the word synchronization signal are input. P and data bits _D29 to _D1 are input. In this case, the input terminal L ₁ becomes “H”, and the input terminal L ₂
may be set to "L" by hardware. Then, in synchronization with the bit clock pulse from the load pulse input timing, the data input to the input terminal _L31 is sequentially input as shown in FIG.
All 32-bit data is output serially. This serial data signal can be e.g. NRZ
(Non Return to Zero) signal, and "H" during bit period T corresponds to "1" and "L" corresponds to "0". The serial data signal from the shift register 2 is input to the OR circuit 3, where it is ORed with the edge inversion signal shown in FIG. 5 from the timing generator 1, and then sent to the AND circuit 4.
sent to. The AND circuit 4 performs a logical product of the inversion inhibit signal shown in FIG. As shown in FIG. 5, this JK input signal is a signal in which "H" and "L" corresponding to data are arranged in the first half T/2 of the bit period T of each bit. The latter half T/2 of each bit becomes "H" due to edge inversion, but only the latter half T/2 of each bit S ₁ and S ₂ corresponding to the above-mentioned inversion inhibition becomes "L". on the other hand,
The clock input terminal of JK flip-flop 5 has
1/ of bit period T from timing generator 1
An FM clock signal with a period of T/2 (a signal whose frequency is twice that of the bit clock) is supplied.
A digital FM output signal as shown in FIG. 5 is obtained from this JK flip-flop 5 and sent to an output terminal 6. That is, the JK flip-flop 5 operates as a digital FM modulator.

Here, the data value of parity bit P is calculated by checking the number of "1"s in data _D1 to _D29 and making sure that the number of "1"s within 30 bits including P is an odd number. However, considering that the bit immediately before bit _S1 of the word synchronization signal portion is always "L", it may be configured such that it is forcibly set to "L" by hardware.

In other words, Figure 6 shows the bits of the word synchronization part.
Rather than forcing the JK input to “H” at the timing just before S ₁ (position P of the JK input in Figure 5),
This shows an example of a circuit configuration for forcibly setting at least the latter half T/2 section of the parity bit P in the FM output to "L". In this FIG. 6, a reset output as shown in FIG. 5 is generated from the timing generator 1, and is supplied to the K input terminal of the JK flip-flop 5 via the OR circuit 7.
Further, the reset output is inverted by an inverter 8 and supplied to the AND circuit 4. Therefore, when this reset output pulse is generated, the J input terminal of the JK flip-flop 5 becomes "L" and the K input terminal becomes "H", so that the second half of the parity bit P becomes T/
The FM output at 2 is forced to "L". In this case, the polarity of the word synchronization signal is absolutely fixed on the transmitting side, but it may be inverted and received on the receiving side, and the polarity -
It does not violate the free conditions.

Next, FIG. 7 shows an example of a circuit configuration on the receiving side (or reproducing side), and the digital FM signal of 1 word of 32 bits is serially input to the input terminal 11 bit by bit. This serial data
The FM signal is sent to an edge detection (inversion detection) circuit 12 consisting of two D-type flip-flops and an exclusive OR circuit. Each D-type flip-flop of the edge detection circuit 12 is supplied with a master clock signal having a frequency six times that of the above-mentioned bit clock via a clock input terminal 13. This master clock signal is supplied to the clock input terminal of a clock counter 14 with a frequency divided by 3.
4 outputs a regenerated FM clock signal with a frequency 1/3 that of the master clock (twice the frequency of the bit clock). In this case, the master clock is generally selected to have a frequency that is an even multiple of six times or more that of the bit clock, and this frequency is divided several times to obtain a reproduced FM clock that is twice that of the bit clock.

Further, the digital FM signal from the input terminal 11 is sent to an FM demodulator (demodulation circuit) 15. This FM demodulator 15 has two D
The FM clock signal from the clock counter 14 is supplied to the clock input terminals of these D-type flip-flops. This FM clock signal is also supplied to the clock input terminal of a divide-by-2 clock counter 16, which outputs a bit clock signal having a frequency that is 1/2 that of the FM clock. This bit clock signal is supplied to the clock input terminal of a D-type flip-flop 17 to which the output signal from the FM demodulator 15 is supplied, and the D-type flip-flop 17 outputs, for example, reproduced serial data of NRZ. Here, the output from the FM demodulator 15 appears as the JK input signal in FIG.
The output from the D-type flip-flop 17 appears as serial data in FIG. This reproduced serial data signal is then sent to the serial-parallel converter 18, where it is converted into a parallel data signal of 1 word of 32 bits (however, the 2 bits S ₁ and S ₂ of the word synchronization part are unnecessary) and output. . This serial-to-parallel converter 18 is supplied with a clock signal from an intra-word timing control circuit 19.

By the way, regarding extraction of the word synchronization signal,
As mentioned above, this is done by detecting that the period from one reversal to the next is 1.5T. A window pulse is used that selectively captures edges within the range. In the example shown in FIG. 7, the master clock signal from the clock input terminal 13 is counted by the word synchronization detection counter 21, and the clock signal is counted over a time range including, for example, the 8th, 9th, and 10th counts from one inversion. The gate circuit 22 generates a window pulse that becomes "H" and sends this window pulse to the AND circuit 23. This AND circuit 23 is supplied with the edge detection pulse from the edge detection circuit 12, and by passing the edge detection pulse only while the window pulse is "H", the edge detection pulse in the word synchronization signal is The inversion (falling edge of the arrow in FIG. 3B) for determining the reference timing is taken out. Here, the edge detection pulse from the edge detection circuit 12 may be supplied to the load terminal (or reset terminal) of the counter 21, but the edge detection pulse 1.5 that may appear from the _latter half of bit S2 to bit _D1 in FIG. The edge detection pulse is supplied to the load terminal of the counter 21 via an AND circuit 24, and the window pulse is supplied to the AND circuit 24 via an inverter 25 so that T is not detected. . That is, the edge detection pulse that detected the reversal (edge) shown by the arrow in FIG.
Supply to 1 is prohibited.

In this way, the edge detection pulse indicating the reference timing in the word signal obtained from the AND circuit 23 is transmitted to each of the aforementioned clock counters 14, 16.
The signal is supplied to the load terminal (or reset terminal) of the memory terminal and the intra-word timing control circuit 19 for synchronization.

Next, FIG. 8 shows a modification of the receiving side circuit of FIG. 7, and the same parts are given the same numbers. According to the circuit configuration shown in FIG. 8, the word synchronization detection counter 31 is connected to the clock counter 14.
It is driven by the FM clock signal, and requires only about 1/3 the speed of the counter 21 in Fig. 7.
As long as you can count up to 3 at 1.5T, it is sufficient. Therefore, the internal configuration of the gate circuit 32 for forming window pulses can also be simplified compared to the gate circuit 22 of FIG. 7. The other configurations may be configured in the same manner as in FIG. 7, but in FIG. 8, the edge detection pulse from the edge detection circuit 12 is used as an input to the load terminal of the clock counter 14, and AND circuit 23,2
The difference from FIG. 7 is that the Q output of the D-type flip-flop on the input side (first stage) of the FM demodulator 15 is used as the input to the FM demodulator 15.

As is clear from the transmitter/receiver circuit examples shown in Figures 4 to 8 above, it can be configured by making only slight changes to the modulation and demodulation circuits of general digital FM systems, and the circuit configuration is simple. Synchronous detection can also be performed reliably and easily.

By the way, in addition to the first, second, and third embodiments whose main parts are shown in FIGS. 3A, B, and C, the DC
For example, a word synchronization signal as shown in FIG. 9 can be used with the -free condition relaxed.

That is, in FIG. 9, the word synchronization signal bit S is set to 1 bit, a parity bit P is provided to keep the polarity unchanged, and only one of the leading edge and trailing edge of the word synchronization signal bit S is set. Reversing is prohibited. In FIG. 9, for example, reversal is prohibited at only one point on the leading edge of bit S, and due to parity bit P, the latter half T/2 of the bit immediately before bit S (parity bit P in FIG. 9) is always on one side. Since the polarity is “H” for example,
A non-inversion section of 1.5T to 2T is obtained. in this case,
Bit S of the word synchronization signal corresponds to “0” and 1
When the word is 32 bits, in order to provide an even number of "0"s including this bit S, the data D ₁ to
An even number of “1”s within the 31 bits of D ₃₀ and parity P are required, resulting in even parity.
can be used as a parity bit.

In the fourth embodiment shown in FIG.
minute) appears only by 1/64 of the peak-to-peak value of the signal waveform, and can be applied to applications where complete DC-free is not required. Furthermore, this fourth embodiment has the advantage that the number of bits for the word synchronization signal is only one bit, and the number of bits for data can be expanded to the maximum.

It should be noted that the present invention is not limited to the above-mentioned embodiments; for example, the number of bits for the word synchronization signal may be 3 or more. In addition, something that has the same effect as the parity bit, such as an error correction code when (X+1) is included in the term when factorizing the polynomial used to calculate data for the error correction code, can be used instead of the parity bit. Good too. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram showing an example of a digital signal modulated by the digital FM method, FIG. 2 is a diagram showing an example of word and block formats of the digital signal applied to the present invention, and FIG. 3 is a diagram showing an example of the format of the digital signal applied to the present invention. FIG. 3A, B, and C are signal waveform diagrams corresponding to the first, second, and third embodiments, respectively, and FIG. 5 is a block circuit diagram showing an example of the transmitting circuit section in the second embodiment, and FIG.
Time chart for explaining the operation of the figure, No. 6
The figure is a block circuit diagram showing a modification of the circuit in FIG. 4, FIG. 7 is a block circuit diagram showing an example of the receiving circuit section in the second embodiment, and FIG. 8 is a modification of the circuit in FIG. 7. FIG. 9 is a signal waveform diagram showing the main part of the fourth embodiment. 1...Timing generator, 2...Shift register, 5...JK flip-flop, 6...
Digital FM signal output terminal, 11...Digital FM signal input terminal, 12...Edge detection circuit,
13...Master clock input terminal, 14, 16
... Clock counter, 15 ... FM demodulator, 17 ... D-type flip-flop, 18 ...
Serial-parallel converter, 21, 31... Counter for word synchronization detection, 22, 32... Gate circuit for forming window pulse.

Claims (1)

[Claims] 1. Digital data in which one word consists of multiple bits 2
In a digital signal transmission method in which value data is digitally modulated and serially transmitted, the above-mentioned digital modulation is performed using the above-mentioned digital 2
It is inverted at the boundary of each bit of value data, and at the center position of each bit, it is inverted when it is the first value,
A modulation rule that does not invert at the second value is adopted, and each word is provided with a word synchronization signal and a parity bit, and the word synchronization signal prohibits inversion at the bit boundary position according to the modulation rule. The total number of bits that take the second value in the digital binary data in one word and the number of the inversion prohibited locations have a pulse width portion that is 1.5 times or more the bit period. A digital signal transmission method characterized in that the value of the parity data is selected such that the sum of the numbers is an even number, and the polarity of the leading edge of the starting end of each word is fixed in the same direction.