JPH11220369A - Clock detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock detecting circuit which can detect whether or not an input clock is present and obtain an optimum detection time by varying the detection time as cycles of an input clock vary. SOLUTION: This clock detecting circuit is equipped with an edge detecting circuit 20 which detects an edge of an input clock Fi with an internal clock Fr, a down counter 30 with a load which receives the edge signal of the edge detecting circuit 20 at its load terminal and outputs a carry signal when having a count value 0, and a flip-flop 40 with a set which receives the carry signal of the down counter 30 with the load at its enable terminal and the edge signal of the edge detecting circuit 20 at its set terminal to detect a clock, and an initial value is loaded to the down counter 30 with the load to detect whether or not the input clock is present.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock detection circuit used for a counter or the like and for detecting the presence or absence of an input clock.

[0002]

2. Description of the Related Art An example of the prior art will be described with reference to FIGS. As shown in FIG. 3, the conventional clock detection circuit includes a one-shot multivibrator 10.

As shown in a timing chart of FIG.
The cycle of the input clock Fi is T1. The one-shot time of each clock of the input clock Fi is set to T2 by the integration circuit of C and R.

If the input clock Fi has a fixed frequency, the period T1 does not change. Therefore, if the range of T2 is the range of the following equation (1), the presence or absence of the input clock can be detected. T1 <T2 <2 · T1 (1) That is, when there is a clock of the input clock Fi, the one-shot periods of the respective clocks overlap each other, the clock detection signal 500 becomes H (High), and the input clock Fi is input. When there is no clock, the clock detection signal 500 becomes L (Low) since there is no one-shot period in each input clock.

However, even if the frequency of the input clock Fi becomes higher and the period T1 becomes shorter, T2 is fixed and constant, so that the detection time for detecting the absence of the input clock Fi is not shortened. Further, when the frequency of the input clock Fi becomes low and the period T1 becomes T1> T2, it is not possible to detect the presence or absence of the clock of the input clock Fi. Further, even when the frequency of the input clock Fi becomes high and the period T1 becomes T2> 2 · T1, it is not possible to detect whether or not the input clock Fi has a clock.

[0006]

As described above, the clock detection circuit using the conventional one-shot multivibrator has a fixed time constant, so that the cycle range in which the input clock Fi changes is limited. Further, there is a practical inconvenience that the detection time for detecting the absence of the input clock is not shortened. Therefore, the present invention has been made in view of such a problem, and an object of the present invention is to make it possible to change the detection time with digital data in response to a change in the cycle of the input clock, and to input the detection time to a desired cycle of the input clock. An object of the present invention is to provide a clock detection circuit which can detect the presence / absence of a clock and obtain an optimum detection time.

[0007]

That is, the first object of the present invention to achieve the above object is to provide an edge detecting circuit for detecting an edge of an input clock by an internal clock, and an edge signal of the edge detecting circuit. The gist of the present invention is a clock detection circuit including a down counter with load that determines a detection time in response to a load, and detects the presence or absence of an input clock.

In order to achieve the above object, a second aspect of the present invention is to provide an edge detection circuit for detecting an edge of an input clock by an internal clock, and a counter for receiving an edge signal of the edge detection circuit at a load terminal. A down counter with a load that outputs a carry signal at 0; a flip-flop with a set that receives a carry signal of the down counter with a load at an enable terminal and receives an edge signal of the edge detection circuit at a set terminal to detect a clock;
The clock detection circuit is characterized in that an initial value is loaded into the down counter with load to detect the presence or absence of an input clock.

In order to achieve the above object, a third aspect of the present invention is to receive an edge signal of an edge detection circuit and a carry signal of a down counter with a load as interrupt signals to a CPU, and determine whether or not an input clock is present. The gist of the present invention is a clock detection circuit according to claim 2 for detecting a clock signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the clock detection circuit of the present invention has an edge detection circuit 20, a down counter 30 with a load, and a flip-flop 40 with a set. The detection time is controlled by the initial value of the control unit 50.

The edge detection circuit 20 includes, for example, a D flip-flop 21 and an EXOR 22. Then, as shown in the timing chart of FIG. 2, the EXOR 22 compares the input clock Fi with the output 100 obtained by latching the input clock Fi with the internal clock Fr, and outputs an edge signal 200. That is, the edge signal 20
0 detects the rising and falling edges of the input clock Fi.

When H (High) of the edge signal 200 is output, since the edge signal 200 is connected to the set terminal S of the flip-flop 40 with a set, the clock detection signal 400 becomes H (High).

Further, the edge signal 200 is connected to a load (LOAD) terminal of the down counter 30 with load.
Then, the initial value set by the control unit 50 is loaded into the down counter 30 with load.

For example, if the initial value n set by the control unit 50 is set to 3, and the H (High) of the edge signal 200 is output due to the rising of the input clock Fi, the down counter 30 with load is set to 3. , Edge signal 200
Becomes L (Low), the count is down-counted every internal clock Fr, and changes to 2, 1, 0.

The down counter 30 with a load is
Before the count number becomes zero, the initial value 3 is loaded by the edge signal 200 due to the falling edge of the input clock Fi.

However, since the edge signal 200 is not output when there is no clock of the input clock Fi, the down counter 30 with a load is down-counted for each internal clock Fr and changes to 2, 1, 0.

When the count of the down counter with load 30 becomes 0, the carry output 3 from the terminal C is output.
00 is output.

The carry output 300 is an enable signal for the flip-flop 40 with a set. Since the data terminal D is fixed at L (Low), the clock detection signal 400 of the flip-flop 40 with the set becomes L (Low) by the internal clock Fr.

Further, when the carry output 300 receives the clock of the input clock Fi and the edge signal 200 is output, the edge signal 200 is connected to the set terminal S of the flip-flop 40 with a set, so that the clock is detected. The signal 400 becomes H (High).

Therefore, when there is a clock of the input clock Fi, the clock detection signal 400 becomes H (High), and when there is no clock of the input clock Fi, the clock detection signal 400 becomes L (Low).

Therefore, in this embodiment, the input clock Fi
Can be arbitrarily changed by setting the initial value of the control unit 50 to a desired value. Further, the clock detection time can be set in a cycle unit of the internal clock Fr. Here, the initial value n
Is obtained by rounding up a fraction of the following equation (2). n = Ti / (2 · Tr) (2) Ti: cycle of input clock Tr: cycle of internal clock

Incidentally, the flip-flop 21 of the edge detection circuit 20 may be an n-stage shift register.
Further, the set-provided flip-flop 40 of the detection unit is a CPU.
And the carry output 300 and the edge signal 200
May be used as an interrupt signal to output a detection signal.

[0024]

The present invention is embodied in the form described above and has the following effects. That is,
A detection time can be changed with respect to a change in the cycle of the input clock, and a clock detection circuit that can detect the presence or absence of the input clock with respect to a desired cycle of the input clock and obtain an optimum detection time can be obtained. it can. Also, by increasing the frequency of the internal clock, the resolution of the detection time can be increased and the clock detection time can be shortened. Further, since the detection time can be set by a digital value, the time can be easily changed, and the circuit can be easily integrated into one chip, so that there is an effect that the circuit can be made strong against a temperature change.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock detection circuit according to the present invention.

FIG. 2 is a timing chart of the clock detection circuit of the present invention.

FIG. 3 is a circuit diagram of a conventional clock detection circuit.

FIG. 4 is a timing chart of a conventional clock detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 One-shot multivibrator 20 Edge detection circuit 21 Flip-flop 22 EXOR 30 Down counter with load 40 Flip-flop with set 50 Control part

Claims (3)

[Claims] 1. An input circuit comprising: an edge detection circuit for detecting an edge of an input clock by an internal clock; and a down counter with a load for receiving an edge signal of the edge detection circuit for a load to determine a detection time. A clock detection circuit for detecting presence / absence. 2. An edge detection circuit for detecting an edge of an input clock by an internal clock, a down counter with a load receiving an edge signal of the edge detection circuit at a load terminal and outputting a carry signal with a count of 0, A flip-flop with a set that receives a carry signal of a down counter at an enable terminal and receives an edge signal of the edge detection circuit at a set terminal to detect a clock, and loads an initial value into the down counter with a load. A clock detection circuit for detecting the presence or absence of an input clock. 3. The clock detection circuit according to claim 2, wherein an edge signal of the edge detection circuit and a carry signal of the down counter with load are received as interrupt signals by the CPU to detect the presence or absence of an input clock.