JPH02284514A - Binary decision circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of chattering even if the timing of an edge is approximated by providing a delay circuit which delays an input pulse signal by the prescribed time to output it when a detection signal is supplied and which outputs the input pulse signal without delaying it in a state that the detection signal is not supplied on the route of a first pulse signal or a second pulse signal. CONSTITUTION:When the pulse signal S1 is supplied from a clock 3, the delay element 15 delays it by the prescribed time T4 and the delayed signal is supplied to one input terminal in an AND circuit 17 as a pulse signal S4. An output signal S3 is supplied to the other input terminal of the AND circuit 17. When a peripheral temperature is low by such a constitution, namely, when the delay time T3 of a pulse signal S2 is longer than a pulse width T1, an output signal S3 goes to a '0' level. When the output signal S3 goes to the '0' level, a signal S5 becomes equal to the signal S1. When the peripheral temperature is high on the other hand, namely, when the delay time T3 of the pulse signal S2 is shorter than the sum of the pulse width T1 and a delay time T4, the output signal S3 goes to a '1' level and the signal S5 becomes equal to the signal S4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a binary judgment circuit that reads the level of one of two pulse signals at the timing of the edge of the other.

``Prior Art'' There are various types of binary decision circuits, but there is one that makes a binary decision by reading the level of one of two pulse signals at the edge of the other. Particularly when this binary decision circuit is used with a device such as a microcomputer that uses a clock signal, the binary decision circuit can be realized with an extremely simple configuration by utilizing this clock signal. As a preferred example, FIG. 3 shows an ambient attitude detection circuit which outputs a signal at the 1 level when the ambient temperature rises, and outputs a signal at the 0 level when the ambient temperature falls.

In FIG. 3, 3 is a clock generator, which outputs a pulse signal Sl of a constant frequency.

A delay circuit 1 includes a thermistor 5, a capacitor 6, and a Schmitt trigger circuit 7.

When the pulse signal S is supplied to the delay circuit 1, the pulse signal S1 is delayed by the thermistor 5 and the capacitor 6. The delayed signal is shaped by the unit trigger circuit 7 and output as a pulse signal S. Here, the pulse signal S2 is a signal delayed from the pulse signal S by a time T3. This delay time T3 is determined by the time constant τ(τ−R
,C,). Here, the capacitance value CI is constant, or the resistance value R1 of the thermistor 5 changes depending on the ambient temperature. Now, when the ambient temperature decreases, the resistance value R
1 becomes larger, and the time constant τ becomes larger. As the time constant τ increases, the delay time T3 also increases. On the other hand, as the ambient temperature increases, the resistance value R1 becomes smaller, the time constant τ becomes smaller, and the delay time T3 becomes smaller. 2 is a D-type flip-flop, a pulse signal S2 is supplied to its D terminal, and a pulse signal S is supplied to its C1, , K terminals. The flip-flop 2 latches the value of the signal S supplied to the D terminal at the falling edge of the pulse signal S1 supplied to the CLK terminal, and outputs this as the output signal S3.
output from the Q terminal as

According to the above configuration, the waveform diagram of each signal when the ambient temperature is high is as shown in FIG. In the figure, the pulse signal S
l is a constant pulse width T, and the period IU de'.

and has. Further, the pulse signal S1 has a standing time T when switching from the °0" level to the '1" level. N
It takes a falling time to switch from the 1' level to the O level. During this rising or falling time, the value of the pulse signal S1 (1' level) is required. Or '0゛.

level) is uncertain. The pulse signal S has the same waveform as the pulse signal S1, and lags behind the pulse signal Sl by a delay time T3. Since it is now assumed that the surrounding LfR is 1 degree or higher, the delay time 1'' is shorter than the pulse width T1. Therefore, at the falling time tA of the pulse signal S1, the pulse signal S2 becomes the "'1" level. The flip-flop 2 latches the value of the pulse signal S at this time and outputs the launched signal as the output signal S3, so the output signal S becomes the level 1.

On the other hand, the waveform diagram of each signal when the ambient temperature is low is as shown in FIG. Since it is now assumed that the ambient temperature is low, the delay time T3 is longer than the pulse width T1. Therefore, at the fall time tB of the pulse signal S, the pulse signal S2 goes to the °'0'" level, so the output signal S3 goes to the °'0" level.

"Problem to be Solved by the Invention" By the way, according to the configuration shown in FIG. 3, when the delay time T3 becomes approximately equal to the pulse width T1, the timing of the fall of the pulse signal S1 and the timing of the rise of the pulse signal S2 coincide. . When the timings match, the flip-flop 2 latches an uncertain value at the rise of the pulse signal S, so it is uncertain whether it is determined to be a "'level" or "o" level. .Therefore, the latched value may change to "1" due to a slight noise entering from the outside.
.

There was a problem of so-called chattering occurring, which frequently fluctuated between the level and "'O" reher.

An object of the present invention is to provide a binary decision circuit that does not cause chattering.

"Means for Solving the Problems j The present invention" - In order to solve the problems described above, a second pulse signal having the same period as the first pulse signal is supplied together with a periodic first pulse signal, - In a binary judgment circuit that outputs a detection signal to the outside when the level of the other pulse signal is at a predetermined level at the rising or falling edge of the pulse signal, when the detection signal is supplied, the The first delay circuit outputs the J pulse signal after being delayed by a certain period of time, and outputs the input pulse signal without delay when the O1i detection signal is not supplied.
or the second pulse signal.

"Operation" The binary determination circuit outputs a detection signal when one of the first and second pulse signals is at a predetermined level when the other pulse signal is at a predetermined level. When the delay circuit is supplied with the detection signal, it delays the input pulse signal by a predetermined time and outputs it, and when it is not supplied with the detection signal, it outputs the input pulse signal without delay.

"Example" Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, the same reference numerals are given to the parts corresponding to those in FIG. 3, and the explanation thereof will be omitted.

In the figure, 4 is a delay circuit, which is composed of a delay element 15, an inverter 16, AND circuits 17 and 18, and an OR circuit 19. When the delay element 15 is supplied with the pulse signal S from the clock 3, it delays it by a certain period of time T4, and outputs the delayed signal as the pulse signal S4 to AN.
It is supplied to one input terminal of the D circuit 17. Also, AND circuit 1
The other input terminal of 7 is supplied with the output signal S3. On the other hand, the AND circuit 18 is supplied with the output signal 93 inverted by the inverter 16 and the pulse signal S1.

The output signals of AND circuits 17 and 18 are sent to OR circuit 19.
The logically added signal is the signal S5.
The signal is supplied to the flip-flop 2 as a signal. According to the above, the signal S5 is expressed by the following logical formula.

S 5-3 a S 4 + S 3S +
......(1) According to equation (1), the output signal S3?
When the output signal S6 is at the '1' level, the signal S6 is equal to the pulse signal S4, and when the output signal S3 is at the '0' level, the signal S6 is equal to the pulse signal S4.
5 is equal to the pulse signal S1.

According to the above configuration, when the ambient temperature is low, that is, when the delay time T3 of the pulse signal S2 is greater than the pulse width T1, the output signal S3 is 0°. When the output signal S3 reaches 0° level, the signal S5 becomes equal to the signal S1, so the temperature detection circuit of this embodiment operates in the same way as the temperature detection circuit of FIG. 3. Therefore, the waveform diagram in this case is as follows. The result is the same as in FIG. 5 when the signal Sl is replaced with the signal S5.

On the other hand, when the ambient temperature is high, that is, when the delay time T3 of the pulse signal S is smaller than the sum of the pulse width T1 and the delay time 'F4, the output signal S3 becomes ``1'' level.Output signal S3 If Billbel is null, signal S5 becomes equal to signal S4.

Next, the operation when the delay time T3 is approximately equal to the pulse width T will be explained with reference to FIG. In the drawings, parts corresponding to those in FIGS. 1, 3 to 5 are designated by the same reference numerals, and their explanations will be omitted. FIG. 2 is a waveform diagram of each signal in FIG. 1. In the figure, pulse signal S4
is the pulse signal S.

This is a signal that has the same waveform as , but is delayed by time T4. The pulse signal S also has the same waveform as the pulse signal SI,
Moreover, it is a signal delayed by a time T3. Delay time T3
is approximately equal to the pulse width T. Here, if the initial value of the output signal S3 is set to 0'' level, the pulse signal S5 becomes equal to the pulse signal S according to equation (1). When this pulse signal s5 is supplied to the CLK terminal of the flip-flop 2, the pulse signal S5 becomes equal to the pulse signal S. The pulse signal S2 is latched at the falling time t of the signal S5. However, since the pulse signal S2 is rising at this point and its value is uncertain,
There are cases in which the flip-flop 2 determines this to be the ``0'' level, and cases in which it determines it to be a bill bell. The operation in both cases will be explained below.

(a) When it is determined that the level is O'°, the flip-flop 2 separates the signal S2 by °'00 and sets the output signal S3 to O' level (see Figure 2).
e) See "D"). When the output signal S3 becomes 0° level, the pulse signal S5 becomes equal to the pulse signal SI (
(See Figure 2 (C)゛C°゛). Therefore, if the pulse signal S2 is latched at the next falling time 1D of the pulse signal S5, an uncertain value will be latched again.

In this way, even if an uncertain value continues to be latched, as long as the flip-flop 2 continues to determine this as the "O°" level, the output signal S3 will stabilize at the "0" level.If the flip-flop 2 , change the latched value once to °゛ 1°“
If the level is determined, the subsequent operation will be similar to the operation described in (b) below.

(b) When the flip-flop 2 determines that the signal S is at the "l" level, the flip-flop 2 sets the output signal S3 to the "bilbel" level (see Figure 2).
When the output signal S3 is set to the level 1, the pulse signal S5 becomes equal to the pulse signal S4 (see FIG. 2(c)). therefore,
When the pulse signal S is latched at the next falling time t, : of the pulse signal S5, the value determined at 1' level is latched. Thereafter, the value determined at the ``1'' level is continued to be latched in the same way, so the output signal S3 becomes ``1''.
“It stabilizes at a level.

Note that even if the delay circuit 4 is inserted between the clock generator 3 and the delay circuit 1 in FIG. 1, the same operation as described above is performed. Furthermore, by changing the configuration of the delay circuit 1, physical quantities other than temperature can be detected. For example, if the thermistor 5 is replaced with a resistor whose resistance value changes depending on the pressure applied from the outside, this pressure can be detected.

It is also possible to provide a binary decision circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a waveform diagram of each signal in FIG. 1, FIG. 3 is a circuit diagram of a conventional ambient temperature detection circuit, and FIG. 4 is a circuit diagram of a conventional ambient temperature detection circuit. FIG. 5 is a waveform diagram of each signal when the ambient temperature is high, and FIG. 5 is a waveform diagram of each signal when the ambient temperature is low in FIG. 2...Flip-flop (binary judgment circuit), 4...Delay circuit.

Claims (1)

[Claims] A second pulse signal having the same period as the first pulse signal is supplied together with a periodic first pulse signal, and when one pulse signal rises or falls, the other pulse signal changes. In a binary judgment circuit that outputs a detection signal to the outside when the level is at a predetermined level, when the detection signal is supplied, the input pulse signal is delayed by a certain period of time and output, and when the detection signal is not supplied. 2. A binary determination circuit, characterized in that a delay circuit that outputs the input pulse signal without delaying the input pulse signal is provided in a path of the first pulse signal or the second pulse signal in the state.