JPH0127609B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit, and particularly to an integrated circuit IC logic circuit.

In an IC logic circuit, the output changes in response to a certain input value, and the input value at this time is called a threshold. Generally, the ratio of change in output to change in input around a threshold is not infinite, so there is a transition region of some width. That is, when the input is in this transition region, the output is not at a logic level. In this sense, the above transition region is referred to as an output-related dead region. If the output is not at a logic level, then the logic circuit cannot perform its original logic function, but if this state continues for a certain period of time, abnormal current may flow through the device or the logic state may become incorrect. In some cases, inconveniences such as inversion may occur, and in such cases, it is necessary to set restrictions such as prohibiting input from staying in the insensitive area for a certain period of time. A conventional example will be explained with reference to FIGS. 1 and 2. Here, an inverter circuit will be explained as an example. The input/output characteristics of the inverter circuit I equipped with the input IN and output OUT shown in Fig. 1 are as shown in Fig. 2. When the input IN is outside the dead area _V1 to _V2 , the output is at level _O1 . When the first logic level has a minimum value or the second logic level has a maximum value of level O ₂ , but is within the dead area V ₁ V ₂ , the minimum value O of the first logic level. ₁ and the second logic level maximum O ₂ , ie not at logic level. Therefore, if the input IN changes logic relatively slowly and stays in the dead area for a long time, the output OUT will remain at the non-logic level O ₁ to
It will continue to be in O ₂ , causing the above-mentioned inconvenience.

It is an object of the present invention to provide a logic circuit with means for detecting when the output is not at a logic level.

In the present invention, the detection means has a first dead area having a smaller value and a second dead area having a larger value than the dead area regarding the output, and the input is between the first and second dead areas. Consisting of a circuit that outputs an output that is at a first logic level at a certain time and is at a second logic level when it is smaller than the first dead area or larger than the second dead area. A reference configuration of the present invention will be described with reference to FIGS. 3 and 4. Here, as an example, a case will be described in which a detection means is provided in an inverter circuit.

As shown in FIG. 3, the logic circuit R consists of an inverter circuit I and a detection means S, and includes an input IN, an inverter output OUT, and an output OS of the detection means S. Input IN is output OUT of inverter circuit I
The output OS of the detection means S is output when the output OUT is not at the logic level in the insensitive region.

Next, the operation will be explained with reference to FIG.

FIG. 4 is a diagram showing input/output characteristics. input
IN is the dead area V ₁ with respect to the inverter output OUT
When at V ₂ , the output OUT is at a non-logic level O ₁ ~
Located in _O2 . The input IN is the first dead area V ₃ to V ₄ or the second dead area V ₅ with respect to the output OS of the detection means S.
~ _V6 , the output OS is at non-logic level _O1 ~
Located in _O2 . Here, the dead area V ₁ ~ _{V 2} is also V ₃ ~
If it is larger than V ₄ and also smaller than V ₅ ~ _{V 6} , when the input IN is in the dead region V ₁ ~ _{V 2} and the output OUT is at the non-logic level O ₁ ~ _{O 2} ,
The output OS is at a first logic level with level O ₁ being the minimum value. That is, the output OS of the detection means S is output. On the other hand, the input IN is at the edge of the dead area V ₃ ~ V ₄ V ₄
When the output OUT is at the _first logic level or _{a second logic} level with the maximum value at level _O2 , the output OS is not at the first logic level, ie the output OS of the sensing means S is not output.

As mentioned above, in a logic circuit equipped with such a detection means, when the output is not at the logic level, a detection output is output to notify the user of this fact, so the detection output can be used to return the device to the reset state, thereby preventing the occurrence of inconveniences. It can be prevented. Therefore, there is no need to impose restrictions such as prohibiting input from staying in an insensitive area for a certain period of time.

Although the above description has been made using an inverter circuit as an example, it is clear that the present invention is also applicable to logic circuits having other functions.

FIG. 5 shows a detection means S as an embodiment of the present invention.
An example of the configuration is shown below. Input IN to exclusive OR circuit EX
and the delay circuit D, and its output DIN is supplied to the other inputs of the exclusive OR circuit EX. Let the output OS of the exclusive OR circuit EX be the output OS of the detection means S. The operation will be explained with reference to FIG. FIG. 6 shows the input/output characteristics. The characteristics of delay circuit D are set as follows.
That is, with respect to the minimum value O ₁ ′ of the input high level and the maximum value O ₂ ′ of the input low level of the exclusive OR circuit EX, if the input IN is equal to or less than the maximum value O ₂ ′ and at the same time, the delay circuit D It is set so that there are input regions V ₇ to V ₈ in which the output DIN is greater than or equal to the minimum value O ₁ '. By setting in this way, when the input IN and the output DIN of the delay circuit D are both low level or both high level, the exclusive OR circuit EX
The output OS is at a low level. On the other hand, when the input IN is at a low level and the output DIN of the delay circuit D is at a high level, that is, when the input IN is in the region _V7 to _V8 , the output OS is at a high level. As described above, a detection means having desired functions can be constructed.

Here, a method for setting the dead area to a desired value will be explained. First, let's consider the inverter circuit. The input/output characteristics near the dead area of the inverter circuit are expressed by equation (1).

V _OUT −V _O =−m(V _IN −V _T )…(1) Here, V _OUT is the output, V _IN is the input, m is the gain, V _O is the center value of the non-logic level, and V _T is the V This is the input value corresponding to _O , that is, the threshold value. In this case, the dead area can be set arbitrarily by selecting V _T and m, or more specifically, if the inverter circuit is configured with two MOS transistors, by selecting the threshold voltage and gm ratio of each. be able to. Next, the input/output characteristics when n stages of inverter circuits are connected are expressed by equations (2) and (3).

V _OUT −V _O = {(−1) ⁿ _o 〓 ⁱ⁼¹ mi}(V _IN −V _T )…(2) Here, mi is the gain of the i-th inverter,
V _K is the threshold value of the Kth inverter. In this case as well, by selecting the characteristics of each inverter, it is possible to arbitrarily set the dead area according to equations (2) and (3).

Generally, logic circuits can be constructed from NAND circuits or NOR circuits, but especially integrated logic circuits are often constructed using the above two basic circuits. It is clear that the above discussion regarding inverter circuits also holds true for these two basic circuits, the NAND circuit and the NOR circuit. The method for setting the dead area to a desired value has been described above.

Next, an example in which the present invention is applied to a memory circuit will be described. The applicant of the present invention has already applied for an invention (Japanese Patent Application No. 54-46848), which is an asynchronous type that does not require an external block, and has a means for detecting a logical change in an address input and at least one address input. A memory circuit has been proposed which includes means for generating an internal clock only when a logic change occurs with respect to the clock. This is an asynchronous type memory circuit that has a speed-power product comparable to that of a synchronous type. A case in which the present invention is applied to the address buffer circuit and internal clock generation circuit of this memory circuit will be explained with reference to FIGS. 7 and 8. First, the memory circuit according to the previously filed invention will be explained. As shown in FIG. 7, this memory circuit includes address buffer circuits B ₀ , B ₁ ...Bn, address decoder circuit DE, memory cell array C, input/output buffer circuit IO, and internal clock generation circuits G ₀ , G _{1 .} ...consists of Gn and G. Address input A ₀ ,
A ₁ ,...An are connected to address buffer circuits B ₀ , B _{1 ,} respectively.
…Each input of Bn and exclusive OR circuit EX ₀ ,
EX ₁ ...Each input and delay circuit D ₀ , D ₁ ... of EXn
In addition to supplying each input of Dn, the delay circuit D ₀ ,
The outputs DA ₀ , DA ₁ ...DAn of each of D ₁ ...Dn are supplied to the other inputs of the corresponding exclusive OR circuits EX ₀ , EX ₁ ...EXn. Exclusive OR circuit EX ₀ , EX ₁ …
The respective outputs OS ₀ , S _{1 .} . . OSn of EXn are input to an OR circuit OR, and the output of the OR circuit OR is input to an inverter circuit I. The outputs CE of the OR circuit OR and the inverter circuit I are internal clocks, and are a reset signal and an enable signal, respectively. The reset signal and enable signal CE are supplied to the address decoder circuit DE, memory cell array C, and input/output circuit IO, respectively. How the internal clock, CE, is generated in the memory circuit having such a configuration will be explained with reference to FIG. Here, as an example, a case will be explained in which the address _A0 undergoes a logical change. When address A ₀ changes logic at time T ₀ , exclusive OR circuit
EX ₀ is the delay signal of address A ₀ DA ₀ is the delay circuit D ₀
Since the logic change does not occur for a period corresponding to the delay time Td, a high level output is generated for a period Td up to time _T1 . This high level output OS ₀
is output as the internal clock CE via the OR circuit OR and the inverter circuit I. After time T ₁ , the delayed output DA ₀ becomes the same logic level as the address A ₀ , and the output OS ₀ becomes a low level. Furthermore, when the level of address A ₀ is restored at time T ₂ , a mismatch occurs again between address A ₀ and its delayed signal DA ₀ over the delay time Td of delay circuit D ₀ until time T ₃ , and the exclusive OR circuit The output OS ₀ of EX ₀ becomes high level and is output as the internal clock, CE.

The above is an explanation of the memory circuit according to the invention already filed. Next, in the memory circuit described above, the address input slowly changes its logic and remains in the dead area for a long period between the minimum value of the input high level and the maximum value of the input low level, that is, the output of the address buffer circuit. Consider the case where the object stays for a long period of time or remains stationary. In such a case, the output of the address buffer circuit remains at a logic level for a long period of time, so if the enable signal CE is output and the address decoder circuit, memory cell array, etc. are in the enabled state, an incorrect address may be accessed. Otherwise, inconveniences such as erroneous writing may occur. Therefore, it can be seen that the memory circuit must be in the reset state when the address input is in this state.

That is, when the address input is in the dead area with respect to the output of the address buffer circuit, the reset signal is
All you have to do is get CE. In order to realize this, it is clear that the present invention can be applied as follows. That is, as shown in FIG. 7, logic circuits R ₀ , R ₁ ...Rn each include address buffer circuits B 0 , B ₁ ...Bn and corresponding _{internal timing generation circuits G 0 ,} G ₁ ...Gn. In contrast, each of the internal timing generation circuits G ₀ , G ₁ , . . . Gn may be set so as to function as a detection circuit according to the present invention.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional example, FIG. 2 is a characteristic diagram of the circuit in FIG. 1, FIG. 3 is a circuit diagram showing a reference example of the present invention, and FIG. 4 is a characteristic diagram thereof. Figure 5 is
A circuit diagram showing a configuration example of the detection means S according to an embodiment of the present invention, FIG. 6 is a characteristic diagram thereof, FIG. 7 is a block diagram of a memory circuit to which the present invention is applied, and FIG. 8 is a timing diagram thereof. It is. IN...Input, I...Inverter circuit, OUT...Inverter output, O ₁ ...Minimum value of the first logic level,
O ₂ ... Maximum value of second logic level, V ₁ , V ₂ ... Output
Both ends of the dead area regarding OUT, R, R ₀ , R ₁ ...
Rn...logic circuit, S...detection means, OS, OS ₀ , OS ₁
...OSn...output of detection means S, V ₃ , V ₄ ...output OS
Both ends of the first dead area regarding V ₅ , V ₆ ...output
Both ends of the second dead area regarding the OS, EX, EX ₀ ,
EX ₁ ...EXn...exclusive OR circuit, D, D ₀ , D ₁
...Dn...Delay circuit, DIN, DA ₀ , DA ₁ ...DAn
…Delay circuit output, O ₁ ′, O ₂ ′…Exclusive OR circuit
Minimum value of input high level and maximum value of input low level of EX, V ₇ , V ₈ ... Input level corresponding to the above O 1 ′, O ₂ ′, A ₀ , _{A 1 ...} An ... Address input, B ₀ ，
B ₁ ...Bn...address buffer circuit, G, G ₀ , G ₁
...Gn...internal clock generation circuit, DE...address decoder circuit, C...memory cell array, 10...input/output buffer circuit, CE...internal clock.

Claims (1)

[Claims] 1 a first logic means that receives an input signal and generates an output; and a minimum high level value of a logic input that receives said input signal and that does not allow said input signal to bring said first logic means to a defined logic level; and a detection means that generates a detection output when the level is between the maximum value of the low level and the output of the first logic means and the detection output; and second logic means that performs an operation based on the output of the logic means and whose operation is prohibited when the detection output is present, and the detection means includes a delay circuit to which the input signal is applied to the input terminal. and,
an exclusive OR circuit, the input signal being applied to a first input terminal, the output signal of the delay circuit being applied to a second input terminal, and the detection output being generated from the output thereof; The sum circuit has a minimum high level value of the logic input and a maximum low level value of the logic input, and the delay circuit has a high level minimum value of the logic input and a low level maximum value of the logic input; A logic circuit having an output range equal to or greater than a minimum value extending between the minimum value and the maximum value.