JPH0618634A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To secure the normal operation in a second inner circuit by delaying the output signal of a first inner circuit at the time of a burn-in activating mode. CONSTITUTION:A delay circuit 5 and a selecting circuit 6 are provided between first and second inner circuits 4a and 4b. An output signal SG of the first inner circuit 4a is delayed in the delay circuit 5 for a specified time. When a burn-in activating signal BE is at an inactive level, the output signal SG of the first inner circuit 4a is selected. When the signal BE is at the active level, the output signal of the delay circuit 5 is selected. The selected signal is transmitted into the second inner circuit 4b with the selecting circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit,
In particular, the present invention relates to a semiconductor memory circuit having an internal circuit which operates in a power supply voltage lower than an external power supply voltage in the normal operation mode and operates in a power supply voltage higher than that in the normal operation mode in the burn-in test mode.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional semiconductor memory circuit of this type.

This semiconductor memory circuit generates an internal reference voltage Vr of a constant voltage lower than the power supply voltage Vcc within a predetermined range in which a power supply voltage Vcc from the outside is lower than a predetermined voltage, and the power supply voltage Vcc is equal to the predetermined voltage. An internal reference voltage generation circuit 1 that generates a burn-in activation voltage Vbe higher than the internal reference voltage Vr when it exceeds, and this internal reference voltage generation circuit 1.
The burn-in activation signal generating circuit 2 which generates the burn-in activation signal BE which becomes the active level in response to the change of the output voltage of the output signal, and the internal reference voltage Vr is selected and activated when the burn-in activation signal BE is inactive. When it is at a level, a voltage switching circuit 3 that selects burn-in activation voltage Vbe, and a first internal circuit 4a that receives the voltage selected by this voltage switching circuit 3 as power supply voltage Vp to operate and output a predetermined signal SG And a second internal circuit 4b that receives the voltage selected by the voltage switching circuit 3 as the power supply voltage Vp, operates, and performs a predetermined process on the transmitted signal SG from the first internal circuit 4a. It is configured to have.

A characteristic diagram of the power supply voltage Vp supplied to the internal circuits 4a and 4b is shown in FIG.

As shown in FIG. 4, the power supply voltage Vc is externally applied.
Within a certain constant range (V1 to V2), the internal power supply voltage Vp is kept at a constant value as the internal reference voltage Vr, the van-in test mode is set, and the power supply voltage Vcc once exceeds a certain level (V2). Then, the power supply voltage Vp becomes the burn-in activation voltage Vbe and increases (decreases in the case of a negative voltage) with respect to the power supply voltage Vcc at a constant rate, and the internal circuit 4
Power supply voltage stress is applied to a and 4b. Normally, when the power supply voltage Vp becomes high, the internal circuit 4a,
The operation speed of 4b becomes faster.

[0006]

In this conventional semiconductor memory circuit, in the burn-in test mode, the power supply voltage Vp higher than that in the normal operation mode is supplied to the internal circuits 4a and 4b. There is a problem that the operation speed becomes faster and the next signal is supplied from the internal circuit 4a before the predetermined processing is completed in the internal circuit 4b, and the normal operation cannot be executed in the internal circuit 4b. .

An object of the present invention is to provide a semiconductor memory circuit capable of ensuring a normal operation in the internal circuit even in the burn-in test mode.

[0008]

The semiconductor memory circuit of the present invention generates an internal reference voltage of a constant voltage lower than the power supply voltage within a predetermined range in which the power supply voltage from the outside is lower than the predetermined voltage. Exceeds the predetermined voltage, an internal reference voltage generation circuit that generates a burn-in activation voltage higher than the internal reference voltage, and a burn-in activation that becomes an active level in response to a change in the output voltage of the internal reference voltage generation circuit. A burn-in activation signal generating circuit for generating a signal; a voltage switching circuit for selecting the internal reference voltage when the burn-in activation signal is at an inactive level and selecting the burn-in activation voltage when at an active level; A first internal circuit that receives a voltage selected by the voltage switching circuit as a power supply voltage and operates to output a predetermined signal; A semiconductor memory circuit having a second internal circuit which receives a voltage selected by a switching circuit as a power supply voltage, operates, and performs a predetermined process on a transmitted signal from the first internal circuit, 1st and 2nd
A delay circuit that delays the output signal of the first internal circuit for a predetermined time between the internal circuits of the first internal circuit and the output signal of the first internal circuit when the burn-in activation signal is at the inactive level. And a selection circuit for selecting the output signal of the delay circuit and transmitting it to the second internal circuit when it is at the active level.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor memory circuit shown in FIG. 3 in that the first and second internal circuits 4 are different.
Between the a and 4b, the resistance elements R1 to Rn and the capacitance elements C1 to
A delay circuit 5 having Cn for delaying the output signal (SG) of the first internal circuit 4a for a predetermined time; and an inverter IV1,
When the burn-in activation signal BE is provided with two transfer gates of the transistors Q1 to Q4, the output signal (SG) of the first internal circuit 4a is selected when the burn-in activation signal BE is at the inactive level (high level) Selects the output signal of the delay circuit 5 to select the second internal circuit 4
The selection circuit 6 for transmitting to b is provided.

First, the external power supply voltage Vcc is the voltage V2.
In the lower normal operation mode, the burn-in activation signal BE is at a low level inactive level, so that the transistors Q1 and Q2 cause the first internal circuit 4a to operate.
Output signal SG is transmitted as it is to the second internal circuit 4b. An internal reference voltage Vr is supplied to these internal circuits 4a and 4b. That is, the signal S
The process for G is executed.

Next, when the burn-in test mode is entered and the external power supply voltage Vcc becomes higher than the voltage V2, the burn-in activation signal BE becomes a high level active level, and the output signal of the delay circuit 5 is selected by the transistors Q3 and Q4. It is transmitted to the second internal circuit 4b. At this time, the power supply voltage Vp of the internal circuits 4a and 4b is higher than that in the normal operation mode. Therefore, the internal circuits 4a, 4
b is operating faster, the signal S of the internal circuit 4a
Although the output timing of G becomes faster, since this signal SG is transmitted to the internal circuit 4b through the delay circuit 5, the next signal is processed after the processing of the previous signal SG in the internal circuit 4b is completed. SG is transmitted. Thus, the internal circuit 4
Normal operation in a and 4b can be ensured.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In this embodiment, the delay circuit 5a is connected to the inverter I
Since it is formed of V51 to IV5m and the basic operation and effect are similar to those of the first embodiment, further description will be omitted.

[0015]

As described above, according to the present invention, the output signal of the first internal circuit is delayed and supplied to the second internal circuit in the burn-in test mode. Therefore, in the burn-in test mode, the internal circuit is delayed. Even if the power supply voltage of the second internal circuit increases and the operating speed of these internal circuits increases, the next signal transmitted from the first internal circuit to the second internal circuit is transmitted with respect to the previous signal in the second internal circuit. After the processing is completed, there is an effect that normal operation in these internal circuits can be ensured.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a conventional semiconductor memory circuit.

4 is a characteristic diagram of a power supply voltage supplied to an internal circuit of the semiconductor memory circuit shown in FIG.

[Explanation of symbols]

 1 Internal reference voltage generation circuit 2 Burn-in activation signal generation circuit 3 Voltage switching circuit 4a, 4b Internal circuit 5, 5a Delay circuit 6 Selection circuit C1 to Cm Capacitive element IV1, IV51, IV5m Inverter Q1 to Q4 Transistor R1 to Rn Resistance element

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/04 B 8427-4M 27/10 481 8728-4M

Claims (3)

[Claims] 1. An internal reference voltage of a constant voltage lower than the power supply voltage is generated within a predetermined range where a power supply voltage from the outside is lower than a predetermined voltage, and the internal reference voltage is generated when the power supply voltage exceeds the predetermined voltage. An internal reference voltage generation circuit that generates a higher burn-in activation voltage, and a burn-in activation signal generation circuit that generates a burn-in activation signal that becomes an active level in response to a change in the output voltage of the internal reference voltage generation circuit, A voltage switching circuit that selects the internal reference voltage when the burn-in activation signal is at the inactive level and selects the burn-in activation voltage when the burn-in activation signal is at the active level, and the voltage selected by the voltage switching circuit is used as the power supply voltage. A first internal circuit that receives and operates to output a predetermined signal, and a voltage selected by the voltage switching circuit as a power supply voltage A second processing for receiving, operating and transmitting the received signal from the first internal circuit
And a burn-in activation signal between the first and second internal circuits, the delay circuit delaying the output signal of the first internal circuit for a predetermined time. A selection circuit for selecting the output signal of the first internal circuit when the signal is at the active level and selecting the output signal of the delay circuit when the signal is at the active level and transmitting the signal to the second internal circuit. And semiconductor memory circuit. 2. The semiconductor memory circuit according to claim 1, wherein the delay circuit is formed of a resistance element and a capacitance element. 3. The semiconductor memory circuit according to claim 1, wherein the delay circuit is formed by an inverter circuit.