KR100370173B1 - Integrated circuit of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit of a semiconductor device suitable for improving the reliability of a burn-in test. A separation unit generating unit, a fuse unit determining whether to repair the memory cell unit, and a first and second word line driver unit respectively controlling the first and second word lines to access data of the memory cell unit during normal operation and test operation, respectively. And a first and second column drivers configured to control data to be output to the outside of the memory cell, and separately drive the normal operation and the burn-in test operation, wherein the bit lines are separated by an output signal of the fuse part. In order to ensure an operating margin between the signal generator and the first and second word line drivers, the signal generator and the first and second word line drivers are different according to the normal operation and the test operation. A mode selector for controlling normal operation and test operation by outputting first and second mode signals having different delay paths to the first and second word line drivers, respectively, and an operation margin between the first and second word lines and the sense amplifier; In order to ensure the normal operation and the test operation is configured to include a sense amplifier driver for controlling the sense amplifier by outputting the sense amplifier activation signal through different delay paths, respectively.

Description

Integrated Circuits in Semiconductor Devices {INTEGRATED CIRCUIT OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to circuits of semiconductor devices, and more particularly, to integrated circuits of semiconductor devices suitable for effectively determining the reliability of devices in carrying out a burn-in test.

In case of the conventional burn-in test, there is sufficient margin between internal signals in the semiconductor device to be activated, so that there is no problem in screening defects caused by defects of the gate oxide film or the oxide-nitride-oxide (ONO), but the semiconductor device is gradually Due to the high speed requirement, the margin between the internal operating signals is reduced even at the normal operating potential, which makes it difficult to determine whether the semiconductor device is defective.

In addition, due to the stress voltage applied to screen the defects of the internal physical properties of the semiconductor device, the operating potential of the circuits in the semiconductor device is increased, so that the mutual margin does not matter at the normal operating potential. Due to the lack of margin between these internal signals before the oxide or ONO material defects are screened, more samples are treated as bad during burn-in mode testing.

Therefore, further testing is performed to verify the margin problem between the series of semiconductor internal operating circuits to determine whether these samples are pure burn-in test failures or samples that failed due to lack of margins of the internal operating signals themselves. The test time consumed to screen for defects increases, and the burn-in test mode, that is, the special test mode for reducing the test time, becomes ineffective.

Hereinafter, an integrated circuit of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1 is a block diagram illustrating an integrated circuit of a semiconductor device for burn-in test.

As shown in Fig. 1, the structure of an integrated circuit of a conventional semiconductor device for burn-in test is a bit line (B) and complement of the memory cell portion 9 for sensing data stored in the memory cell portion 9; A bit line split signal for selecting one of two sense lines 10 connected to the bit line B / and a row active signal received from the outside, and selecting two bit lines shared by the sense amplifier 10. A fuse line for outputting the fuse signals and the second address signal by determining whether to repair the selected memory cell unit 9 based on the low active signal and the first address signal; 8) a mode selector 7 which receives the low active signal and the fuse signals and selectively outputs the first mode signal for the test operation and the second mode signal for the normal operation, and the low active signal in common. First and second word line driving signals to receive the first and second mode signals and to enable the first and second word lines WL1 and WL2 to access the data of the memory cell unit 9, respectively. The first and second word line drivers 2 and 6 respectively outputting the sense amplifier driver 4 outputting a sense amplifier activation signal by a low active signal, and the first and second words by receiving a low active signal. And first and second column drivers 1 and 5 respectively outputting first and second column active signals to output data of the memory cell unit 9 corresponding to the lines WL1 and WL2 to the outside. .

Here, the first word line driver 2 accesses the data of the memory cell unit 9 selected by the first address signal to normally sense the second word line driver 6 by the second address signal. Access is made to test the data of the selected memory cell section 9.

The operation of the integrated circuit of the conventional semiconductor device is as follows.

2 is a signal waveform diagram illustrating the normal operation of the integrated circuit of the conventional semiconductor device, and FIG. 3 is a signal waveform diagram illustrating the test operation of the integrated circuit of the conventional semiconductor device.

The fuse unit 8 receiving the low active signal and the first address signal determines whether or not the wordline repair fuse of the memory cell unit 9 selected by the first address signal is repaired. The mode selector 7 determines the normal operation or the test operation by the output signal of the fuse 8.

First, as shown in FIG. 2, the mode selector 7 outputs the low level second mode signal by the output signal of the fuse unit 8 that receives the address of the repaired memory cell unit 9. In operation, the bit line separation signal generator 3 receiving the low active signal from the outside outputs the bit line separation signal to select one of two bit lines shared by the sense amplifier 10.

Subsequently, the second word line driver 6 receiving the low level second mode signal from the mode selector 7 is turned off and is driven by the first mode signal maintained at the high level. When (2) enables the first word line WL1 by outputting the first word line driving signal, the data of the memory cell unit 9 is accessed through the bit line.

The sense amplifier driver 4 outputs a sense amplifier activation signal so that the sense amplifier 10 senses data of the memory cell unit 9 loaded on the bit line.

On the contrary, as shown in FIG. 3, the mode selector 7 outputs the low level first mode signal by the output signal of the fuse unit 8 that receives the address of the unrepaired memory cell unit 9. In the burn-in test operation, the bit line isolation signal generator 3 receiving the low active signal from the outside selects one of two bit lines shared by the sense amplifier 10. Outputs

Subsequently, the first word line driver 2 receiving the low level first mode signal from the mode selector 7 is turned off and the second word line driver is driven by the second mode signal maintained at the high level. 6 outputs a second word line driving signal, and when the second word line WL2 is enabled, data of the memory cell unit 9 is accessed as a bit line.

The sense amplifier driver 4 outputs a sense amplifier activation signal so that the sense amplifier 10 senses data of the memory cell unit 9 loaded on the bit line.

In the above test operation, when the second word line WL2 is enabled before the bit line B and the complementary bit line B / are selected by the bit line separation signal, the data of the stored memory cell unit 9 is stored. An error occurs by transitioning to the precharge voltage level.

In addition, if the sense amplifier 10 is activated before the data of the memory cell unit 9 is sufficiently loaded on the selected bit line, an error is generated by amplifying the data in reverse.

4 is a circuit diagram for explaining a mode selection unit 7 of an integrated circuit of a conventional semiconductor element.

As shown in FIG. 4, the conventional mode selector 7 inverts the first inverter 21 for inverting the low active signal input from the outside and the inverted output signal of the first inverter 21 to output the same. Second inverter 22, a delay unit 23 for delaying and outputting the output signal of the second inverter 22, a third inverter 24 for inverting the output signal of the delay unit 23, The first NOR gate 25, which calculates and outputs the output signals of the first inverter 21 and the third inverter 24, and the first, second, third, and fourth fuse signals output from the fuse unit 8. A second NOR gate 26 that calculates and outputs the second NOR gate 26, a fourth inverter 27 that inverts and outputs an output signal of the second NOR gate 26, and the first NOR gate 25 and the fourth inverter A NAND gate 28 for calculating and outputting the output signal of (27) and a first mode signal for delaying the output signal of the NAND gate 28 and outputting a first mode signal; A first inverter unit 29a and a second inverter unit 29b for delaying the output signal of the fourth inverter 27 and outputting a second mode signal.

When the first, second, third, and fourth fuse signals input to the NOR gate have a high value, the conventional mode selector 7 outputs a low level first mode signal to perform a test operation. If all of the first, second, third, and fourth fuse signals have a low value, the second mode signal of a low level is output to perform normal operation.

However, in the normal operation, if the fuse signal calculated by the second NOR gate 26 is not enabled before the low active signal to the NAND gate 28, the first mode signal having a low level is output and a predetermined time is output. After the elapsed time, when the fuse signal arrives, the second mode signal is output at a low level to proceed with normal operation.

Therefore, an error occurs by performing a test operation and a normal operation in one low active period.

FIG. 5 is a circuit diagram illustrating a sense amplifier driver 4 of an integrated circuit of a conventional semiconductor device, and FIG. 6 is a signal waveform diagram illustrating an operation of the conventional sense amplifier driver 4.

As shown in FIG. 5, the conventional sense amplifier driver 4 receives first and second delay units 31 and 32 for receiving a low active signal and delaying a predetermined time, respectively, and the first and second delays. And a NAND gate 33 for calculating the output signals of the units 31 and 32, and an inverter unit 34 for inverting the output signals of the NAND gate 33 and outputting the inverted signals.

As shown in FIG. 6, in the normal operation of the sense amplifier driver 4, the time required for the data of the memory cell unit 9 to be sufficiently loaded on the bit line after the first word line WL1 is enabled, For example, when the data of the memory cell unit 9 is high, +100 mV, and when low, -100 mV, the sense amplifier activation signal is output after a time required to increase or decrease at the bit line precharge level.

However, if the output of the sense amplifier activation signal is excessively delayed and output in order to secure the time for the data of the memory cell unit 9 to be loaded on the bit line, the operation speed of the device is reduced.

On the contrary, during the burn-in test operation, after the second word line WL2 is enabled, the operation potential is increased to accelerate the activation time of the sense amplifier 9 so that the data of the memory cell unit 9 is sufficiently loaded on the bit line. Since the sense amplifier 10 is driven before, an error that is amplified by the data opposite to the stored data occurs.

In addition, the trouble of modifying the test program to make it output after the stored data is sufficiently sensed occurs.

However, the integrated circuit of the conventional semiconductor device as described above has the following problems.

First, by using signals having the same delay time as the normal operation in the burn-in test operation, the normal memory cell is also treated as defective due to lack of margin between the signals.

Second, the test time required for adding a test procedure for retesting a memory cell that is determined to be defective due to lack of margin between signals becomes long.

The present invention is to solve the problems of the integrated circuit of the conventional semiconductor device, the integrated circuit of the semiconductor device suitable for securing the operating margin by differently forming the internal delay path of the signals activated during the burn-in test operation and normal operation The purpose is to provide.

1 is a block diagram illustrating an integrated circuit of a semiconductor device for burn-in test

2 is a signal waveform diagram illustrating a normal operation of an integrated circuit of a conventional semiconductor device.

3 is a signal waveform diagram for explaining a test operation of an integrated circuit of a conventional semiconductor device.

4 is a circuit diagram illustrating a conventional mode selection unit.

5 is a circuit diagram illustrating a conventional sense amplifier driver.

6 is a signal waveform diagram for explaining an operation of a conventional sense amplifier driver.

7 is a circuit diagram for explaining a mode selection unit according to the present invention.

8 is a circuit diagram illustrating a sense amplifier driver according to the present invention.

9 is a signal waveform diagram for explaining the operation of the sense amplifier driver according to the present invention.

10 is a view illustrating an operation time of a sense amplifier driver according to the present invention.

Explanation of symbols for the main parts of the drawings

1: first column driver 2: first word line driver

3: bit line separation signal generator 4: sense amplifier driver

5: second column driver 6: second word line driver

7: Mode selector 8: Fuse

9: memory cell unit 10: sense amplifier

71,72: first and second delay units 73,74: first and second NOR gates

75,84: first transfer gate 76,85: second transfer gate

77: NOR calculator 78,87: NAND calculator

79a, 79b: first and second mode signal output terminals 81,82,83: first, second and third signal delay units

88: inverter unit

In accordance with one aspect of the present invention, an integrated circuit of a semiconductor device includes a sense amplifier connected to a bit line and a complementary bit line of a memory cell unit, and a bit line separation signal generator for selecting one of the bit line and the complementary bit line. A fuse unit for determining whether to repair the memory cell unit, a first word line driver for controlling the first and second word lines to access data of the memory cell unit during normal operation and a test operation, respectively, and a memory cell unit A circuit including first and second column drivers configured to control data to be output to the outside, wherein the circuit is configured to separately drive normal operation and burn-in test operation. The first and second word line drivers have different delay paths according to normal operation and test operation to ensure an operating margin. A mode selector for controlling normal operation and test operation by outputting first and second mode signals to the first and second word line drivers, and normal operation to secure an operation margin between the first and second word lines and a sense amplifier; And a sense amplifier driver configured to control the sense amplifier by outputting a sense amplifier activation signal through different delay paths during the test operation.

Hereinafter, an integrated circuit and an operation thereof of a semiconductor device of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating an integrated circuit of a semiconductor device for burn-in test.

As shown in FIG. 1, an integrated circuit of a semiconductor device according to the present invention includes a bit line B and a complementary bit line B / of the memory cell unit 9 for sensing data stored in the memory cell unit 9. A bit line separation signal generator for receiving a low active signal from an external device and a bit line separation signal to select one of two bit lines shared by the sense amplifier 10; 3) a fuse unit 8 which determines whether to repair the memory cell unit 9 selected by the low active signal and the first address signal, and outputs fuse signals and a second address signal; and a low active signal and a fuse signal. First and second mode signals for controlling the normal operation and the test operation through different delay paths so as to secure a margin between the operation signal between the bit line separation signal generator 3 and the word line. The first and second word lines WL1 for selectively outputting the mode selector 7 and the low active signal in common and receiving the first and second mode signals respectively to access the data of the memory cell unit 9. First and second word line drivers 2 and 6 for outputting first and second word line driving signals to enable WL2, respectively, and first and second word lines WL1 receiving low active signals; In order to secure an operating margin between the WL2 and the sense amplifier, a sense amplifier driver 4 for outputting a sense amplifier activation signal by varying a delay path during normal operation and a test operation, and a low active signal are received. First and second column drivers 1 and 5 respectively outputting first and second column active signals to output data of the memory cell unit 9 corresponding to the two word lines WL1 and WL2 to the outside. It is composed.

Referring to the operation of the integrated circuit of the semiconductor device according to the present invention as follows.

The fuse unit 8 receiving the low active signal and the first address signal determines whether or not the wordline repair fuse of the memory cell unit 9 selected by the first address signal is repaired. The mode selector 7 determines the normal operation or the test operation based on the output signal of the fuse 8.

First, in the normal operation, the bit line separation signal generator 3 receiving the low active signal from the outside outputs the bit line separation signal to select one of two bit lines shared by the sense amplifier 10. do.

Then, the mode selector 7 outputs the low level second mode signal by the output signal of the fuse unit 8 that receives the address of the repaired memory cell unit 9 to proceed with normal operation.

Subsequently, the second word line driver 6 receiving the low level second mode signal from the mode selector 7 is turned off and is driven by the first mode signal maintained at the high level. When (2) enables the first word line WL1 by outputting the first word line driving signal, the data of the memory cell unit 9 is accessed through the bit line.

The sense amplifier driver 4 outputs a sense amplifier activation signal such that the sense amplifier 10 senses data of the memory cell unit 9 loaded on the bit line, and the first column driver 1 outputs the first column active signal. And outputs the data of the memory cell unit 9 corresponding to the first word line WL1 to the outside.

On the contrary, in the test operation, the bit line separation signal generator 3 receiving the low active signal from the outside outputs the bit line separation signal to select one of two bit lines shared by the sense amplifier 10. do.

The mode selector 7 outputs the low level first mode signal in response to the output signal of the fuse unit 8 that receives the address of the unrepaired memory cell unit 9 to perform a test operation.

Subsequently, the first word line driver 2 receiving the low level first mode signal from the fuse 8 is turned off and the second word line driver 2 is driven by the second mode signal maintained at the high level. 6) outputs a second word line driving signal, and when the second word line WL2 is enabled, data of the memory cell unit 9 is accessed as a bit line.

The sense amplifier driver 4 outputs a sense amplifier activation signal such that the sense amplifier 10 senses data of the memory cell unit 9 loaded on the bit line, and the second column driver 5 outputs the second column active signal. And outputs the data of the memory cell unit 9 corresponding to the second word line WL2 to the outside.

7 is a circuit diagram for explaining the mode selection section 7 of the integrated circuit of the semiconductor device according to the present invention.

As shown in FIG. 7, the mode selector 7 according to the present invention includes a test operation delay unit 710 and a normal operation delay unit 720 for delaying and outputting a low active signal at different delay times; A first transfer gate 75 for switching the output signal of the test operation delay unit 710 according to the burn-in signal and the inverted burn-in signal output from the test mode decoder (not shown), and the burn-in signal And the second transmission gate 76 for switching the output signal of the normal operation delay unit 720 according to the inverted burn-in signal, and the first, second, third, and fourth fuse signals output from the fuse unit 8. A NOR calculator 77 for calculating and outputting, a NAND calculator 78 for calculating and outputting an inverted output signal of the NOR calculator 77 and an output signal of the first and second transfer gates 75 and 76; And a first mode signal outputting a first mode signal by delaying an output signal of the NAND calculator 78. An output terminal 79a and a second mode signal output terminal 79b for delaying the inverted output signal of the NOR calculator 77 to output the second mode signal.

The test operation delay unit 710 may include a first inverter IN1 for inverting a low active signal, a second inverter IN2 for inverting an output signal of the first inverter IN1, and the second inverter. A first delay unit 71 for delaying the output signal of IN2, a third inverter IN3 for inverting the output signal of the first delay unit 71, the first inverter IN1 and a third It consists of a 1st NOR gate 73 which computes and outputs the output signal of inverter IN3.

In addition, the normal operation delay unit 720 may include a fourth inverter IN4 for inverting the low active signal, a fifth inverter IN5 for inverting the output signal of the fourth inverter IN4, and the fifth inverter ( A second delay unit 72 for delaying the output signal of IN5; a sixth inverter IN6 for inverting the output signal of the second delay unit 72; and a fourth inverter IN4 and a sixth inverter. It consists of a 2nd NOR gate 74 which computes and outputs the output signal of IN6.

As described above, the mode selector 7 according to the present invention has a low level second to proceed with normal operation when the first, second, third, and fourth fuse signals input to the NOR calculator 77 have a low value. Outputs the mode signal.

At this time, the low active signal input from the outside is input to the NAND calculator 78 through the normal operation delay unit 720 is delayed to be input to the NAND calculator 78 later than the output signal of the NOR calculator 77.

In addition, when at least one of the first, second, third, and fourth fuse signals input to the NOR calculator 77 has a high value, a test operation is performed. At this time, a low active signal input from the outside is a test operation delay unit. After the predetermined time delay through the 710 is input to the NAND calculator 78, the NAND calculator 78 receives the output signal of the test operation delay unit 710 and the NOR operator 77 is a low level Outputs 1 mode signal.

Here, the output signals of the test operation delay unit 710 and the normal operation delay unit 720 are selectively output by the burn-in signal input from the outside.

FIG. 8 is a circuit diagram illustrating a sense amplifier driver of an integrated circuit of a semiconductor device according to the present invention. FIG. 9 is a signal waveform diagram illustrating an operation of the sense amplifier driver of the present invention. Is a view showing an operation time point of the sense amplifier driver according to the present invention.

As shown in FIG. 8, the sense amplifier driver 4 of the present invention includes first, second, and third signal delay units 81, 82, 83 for delaying low active signals with different delay times, respectively; A first transmission gate 84 for switching the output signal of the first signal delay unit 81 according to the burn-in signal and the inverted burn-in signal, and Compute the second transmission gate 85 for switching the output signal of the two signal delay unit 82, and the output signals of the third signal delay unit 83 and the first and second transmission gates 84, 85. And an inverter unit 88 for inverting the output signal of the NAND calculator 87.

As shown in FIG. 9, in the normal operation of the sense amplifier driver 4, the data of the memory cell unit 9 may be sufficiently loaded on the bit line after the first word line WL1 is enabled. After the time required for consumption, the sensor outputs the sense amplifier activation signal.

In this case, the low active signal input from the outside is input to the NAND calculator 87 through the second signal delay unit 82 to output a sense amplifier activation signal.

On the contrary, in the burn-in test operation, after the second word line WL2 is enabled, the operating potential is increased to increase the time at which the sense amplifier 10 is activated, before the memory cell unit 9 data is sufficiently loaded on the bit line. Since the sense amplifier 10 is driven, the delay of the data of the memory cell unit 9 is sufficiently loaded on the bit line using the first signal delay unit 81 and then the sense amplifier activation signal is output.

Here, the output signals of the first signal delay unit 81 and the second signal delay unit 82 are selectively output by the burn-in signal input from the outside.

The integrated circuit of the semiconductor device of the present invention as described above has the following effects.

First, the operation margin between the signals activated according to the normal operation and the test operation is secured differently, thereby preventing the defect due to the operation margin during the burn-in test, thereby improving reliability of the burn-in test.

Second, by reducing the error of burn-in test due to the operating margin, it is possible to reduce the test time added due to recheck.

Claims (5)

A sense amplifier connected to the bit line and the complementary bit line of the memory cell unit, a bit line separation signal generator for selecting one of the bit line and the complementary bit line, a fuse unit for determining whether to repair the memory cell unit, normal operation and test First and second word line drivers for controlling the first and second word lines, respectively, to access the data of the memory cell unit during operation, and first and second column drivers for controlling the output of data of the memory cell unit to the outside; In the circuit for driving the normal operation and the burn-in test operation separately, In order to secure an operating margin between the bit line separation signal generator and the first and second word line drivers by the output signal of the fuse unit, first and second mode signals having different delay paths according to normal operation and test operation are respectively applied. A mode selector for outputting the first and second word line drivers to control normal operation and test operation, respectively; And a sense amplifier driver for controlling the sense amplifier by outputting sense amplifier activation signals through different delay paths during normal operation and test operation, respectively, in order to secure an operation margin between the first and second word lines and the sense amplifier. An integrated circuit of a semiconductor device, characterized in that. The apparatus of claim 1, wherein the mode selector comprises a test operation delay unit and a normal operation delay unit delaying the low active signal with different delay times, and a burn-in signal and an inverted burn-in signal input from an external device. First and second transfer gates for switching the output signals of the test operation delay unit and the normal operation delay unit to be selectively output, and a NOR operation unit for calculating the first, second, third and fourth fuse signals output from the fuse unit; A NAND calculator for calculating an inverted output signal of the NOR calculator and an output signal of the first and second transfer gates, a first mode signal output terminal for delaying an output signal of the NAND calculator and outputting a first mode signal, and the NOR And a second mode signal output terminal for delaying the inverted output signal of the calculating unit and outputting a second mode signal. The method of claim 2, wherein the test operation delay unit comprises: a first inverter for inverting a low active signal; a second inverter for inverting an output signal of the first inverter; and a first delay for delaying an output signal of the second inverter. And a third inverter for inverting the output signal of the first delay unit, and a first NOR gate for calculating the output signals of the first and third inverters, wherein the normal operation delay unit inverts the low active signal. A fourth inverter to be inverted, a fifth inverter to invert the output signal of the fourth inverter, a second delay unit to delay the output signal of the fifth inverter, and a sixth inverter to invert the output signal of the second delay unit. And a second NOR gate for calculating output signals of the fourth inverter and the sixth inverter. The semiconductor device of claim 1, wherein the mode selector is configured to output a low level first mode signal to perform a test operation and to output a low level second mode signal to perform a normal operation. integrated circuit. The method of claim 1, wherein the sense amplifier driver comprises first, second, and third signal delay units for delaying the low active signal with different delay times, and the first, second, and third signals according to the burn-in signal and the inverted burn-in signal. First and second transfer gates for switching to selectively output the output signals of the two signal delay units, a NAND calculator for calculating and outputting the output signals of the third signal delay unit and the first and second transfer gates, and the NAND And an inverter unit for inverting an output signal of the computing unit.