KR100849776B1 - Semiconductor memory device having DQ compress circuit - Google Patents

Abstract

The semiconductor memory device including the DQ compression circuit according to the present invention further includes a comparison means for comparing the data stored in the plurality of memory cells with the data loaded in the plurality of global write I / O lines, and the plurality of global write I / O lines. And a control means for outputting a control signal by using a plurality of switching means for setting a high level to a high level and a signal for distinguishing between a read operation and a write operation to control the plurality of switching means. Since the written data can be compared with the data stored in the memory cell and read, the logical errors occurring during the test operation can be corrected, thereby reducing the test time of the memory device and improving the yield.

Description

Semiconductor memory device having DQ compression circuit

1 is a circuit diagram showing a major part of a semiconductor memory device including a DQ compression circuit according to the prior art.

2 is a circuit diagram illustrating a write path in a semiconductor memory device including a DQ compression circuit according to the prior art.

3 is a circuit diagram showing a major part of a semiconductor memory device including a DQ compression circuit according to the present invention.

<Description of Symbols for Major Parts of Drawings>

11: bank

12 to 15: memory cell array block

16: switching unit

17: control unit

EXNOR11-EXNOR30: Exclusive NOR

AND11: AND gate

INV11: Inverter

ND11: Nand Gate                 

PM1-PM4: PMOS transistor

DQ0: I / O pad

GWIO: Global Light Input / Output Line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device including an input / output (hereinafter referred to as DQ) compression circuit. More particularly, the present invention further includes a circuit for comparing the written data with the read output to correct a logical error. A semiconductor memory device including a DQ compression circuit capable of reducing test time of a memory device and improving a yield.

1 is a circuit diagram illustrating a main part of a semiconductor memory device including a DQ compression circuit according to the prior art. Here, the case where the bank 1 is comprised by four 16M memory blocks 2-5 is demonstrated as an example.

The DQ compression circuit logically multiplies the outputs of the four exclusive NOR gates EXNOR1 to EXNOR4 and four outputs of the four exclusive NOR gates EXNOR1 to EXNOR4 that perform four exclusive NOR operations on fourteen input / output lines in the bank 1. And gate AND1 output to the pad DQ0.

Data carried on four I / O lines is input to the exclusive NOR gate EXNOR1, and only when all four data are the same, the final output is passed at a low level, and conversely, any one of the data carried on the four I / O lines. If different, the final output goes high and fails.

In order to perform the test in this manner, the same global write I / O when the data input through the write path as shown in FIG. 2, that is, the input / output pad DQ0 is driven by the input driver 6 and is in the compression mode, is used. The same data must be entered via the line GWIO. That is, the same data is written to all memory cells, and the stored data is read and tested for the same.

However, if, for example, data of "0" is stored through the input / output lines GWIO0, GWIO2, GWIO4, and GWIO6, read through the input / output lines GRIO0, GRIO2, GRIO4, GRIO6 due to a defect in the memory cell or a malfunction of other peripheral circuits. If all the data is "1", the output of the corresponding exclusive no-gate goes to a high level and passes. That is, there is a problem in that an incorrect test result is derived because the defect of the memory cell is not properly screened.

An object of the present invention for solving the above problems is to compare the written data and the data at the read time and combine the results and output them through the input / output pad to correct the logical error to reduce the test time of the memory.

A semiconductor memory device including the DQ compression circuit of the present invention for achieving the above object,                     

A plurality of banks composed of a plurality of memory cell array blocks including a plurality of memory cells;

A plurality of global write input / output lines for transmitting data for storing in the memory cell array;

A plurality of first comparison means for comparing data stored in the plurality of memory cells with data loaded in the plurality of global write I / O lines, respectively;

A plurality of second comparing means for comparing a predetermined number of outputs of the plurality of first comparing means;

A plurality of switching means for setting the plurality of global light input / output lines to a high level; And

And control means for outputting a control signal for controlling the plurality of switching means.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram illustrating a DQ compression circuit according to the present invention. Here, the case where one bank 11 consists of four memory cell array blocks 12-15 is demonstrated as an example.

The DQ compression circuit uses four exclusive Noah gates EXNOR15 to EXNOR30 and four exclusive Noagate EXNOR15 to EXNOR30 outputs for comparing the data carried in the 16 input / output lines in the bank 11 and the four global write I / O lines GWIO. A high level VCC is selectively applied to the global light I / O line GWIO and the AND gate AND11 for logically multiplying the outputs of the four exclusive Noah gates EXNOR11 to EXNOR14 to be calculated, the outputs of the four exclusive Noah gates EXNOR11 to EXNOR14, and outputting them to the I / O pad DQ0. And a control unit 17 for outputting a control signal SWC for controlling the switching unit 16.

Here, the switching unit 16 includes four PMOS transistors PM1 to PM4 for applying the control signal SWC to the gate to selectively apply the high level VCC to each of the global write input / output lines GWIO.

The controller 17 is the inverter INV11 which inverts the special test mode signal STMWVR, which becomes a high level only when the write-verify-read operation in the special test mode, and the special test mode signal inverted by the inverter INV11. And the NAND gate ND11 that outputs the control signal SWC by performing a negative logical multiplication on the / STMWVR and the operation selection signal / RDWT indicating the read operation and the write operation.

In addition, the exclusive Noah gates EXNOR15 to EXNOR30 are used for the purpose of comparing the written data with the read data. That is, it compares whether the data loaded on the global write I / O line GWIO and the data stored and read in the memory cell are the same.

Here, a place for storing data written on the global write input / output line GWIO is stored using a memory device such as a data bus line, a separate memory cell, or a flip-flop.

Referring to the operation of the DQ compression circuit according to the present invention configured as described above in detail as follows.

First, in the case of the write-verify-read operation of the special test mode and the special test mode DQ compression operation, the control signal SWC is high level regardless of whether the current operation is the write or read operation. All PMOS transistors PM1 to PM4 of the switching unit 16 are turned off.

Therefore, in the write operation, data is written through the global write I / O line GWIO, and data loaded on the global write I / O line GWIO is maintained using a separate memory means while there is no next write command.

In the read operation, data stored in a memory cell is read and applied to one input terminal of the exclusive NOR gates EXNOR15 to EXNOR30, and data loaded on the global write I / O line GWIO is applied to the other input terminal. Outputs a low level signal.

In addition, the exclusive Noah gates EXNOR11 to EXNOR14 combine four output signals of the exclusive Noah gates EXNOR15 to EXNOR30, and when all high level signals are inputted, the high level signals are output to pass the judgment. If there is, a low level signal is output to fail.

On the other hand, in the case of the special test mode DQ compression operation, not the write-verify-read operation of the special test mode, the PMOS transistors PM1 to PM4 of the switching unit 16 are turned on during the read operation. In the write operation, the PMOS transistors PM1 to PM4 of the switching unit 16 are turned off.

Therefore, during the write operation, data is written to the memory cell through the global write I / O line GWIO, and during the read operation, the PMOS transistors PM1 to PM4 of the switching unit 16 are turned on, so that the global write I / O lines GWIO are all high-level. Since it is set to VCC, the exclusive NOR gates EXNOR15 to EXNOR30 simply serve to transfer the data stored and read in the memory cell.

That is, the exclusive Noah gates EXNOR11 to EXNOR14 compare four data read and stored in the memory cell and output a high level when all are identical, and pass a low level when any one is different, and fail. Determine.

As described above, the DQ compression circuit according to the present invention compares data carried on a plurality of different input / output lines during a read operation, stores data read through the global write input / output lines and stored in the memory cell array. The data can be compared, which corrects the logical errors that occur during test operations, thereby reducing the test time of the memory and improving the yield.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.

Claims (5)

A plurality of banks composed of a plurality of memory cell array blocks including a plurality of memory cells; A plurality of global write input / output lines for transmitting data for storing in the memory cell array; A plurality of first comparison means for comparing data stored in the plurality of memory cells with data loaded in the plurality of global write I / O lines, respectively; A plurality of second comparing means for comparing a predetermined number of outputs of the plurality of first comparing means; A plurality of switching means for setting the plurality of global light input / output lines to a high level; And And a control means for outputting a control signal for controlling said plurality of switching means. The method of claim 1, And said first comparing means and said second comparing means comprise exclusive logic gates. The method of claim 1, And said switching means comprises a MOS transistor. The method of claim 1, The control means, And a logic gate for outputting the control signal by a logical combination of a signal distinguishing a read operation from a write operation and a signal representing a special test mode. The method of claim 1, And a data loaded on the global write I / O line is stored in any one of a data bus line, a memory cell, and a flip-flop.

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