KR20130131992A - Test circuit and method of semiconductor memory apparatus - Google Patents

Abstract

A test circuit of a semiconductor memory device, at a first test mode, compares and compresses data stored at a plurality of memory cells within a memory bank to generate the compressed data and outputs the compressed data as test data to an IO pad via one selected global line. And the test circuit, at a second test mode, transmits the compressed data to a plurality of global lines, combines each of the compressed data carried on the global lines, and outputs the combining result as the test data to the IO pad. [Reference numerals] (10) First bank;(20) Second bank;(30) First compressor;(40) Second compressor;(50) Combination output part;(60) First switch;(70) Second switch

Description

TEST CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS}

The present invention relates to a semiconductor memory device, and more particularly, to a test circuit and a test method of a semiconductor memory device.

1 is a block diagram of a general semiconductor memory device.

The semiconductor memory device may include a plurality of memory banks for storing data in memory cells, and may write data to the respective memory banks through input / output pads, or read data stored in the respective memory banks through the input / output pads. have.

As shown in FIG. 1, the semiconductor memory device includes a first bank 1, a second bank 2, and an output unit 5. Data stored in a plurality of memory cells in the first bank 1 and the second bank 2 are transmitted to the output unit 5 via a global line GIO <0: 3>. That is, since the first bank 1 and the second bank 2 share a global line GIO <0: 3>, the first bank 1 and the second bank 2 share a global line GIO <0: 3>. Access is possible. The output unit 5 sorts the data transmitted through the global lines GIO <0: 3> and outputs the data to the outside through the input / output pads DQ <0: 1>. In an embodiment, the data on the first and second global lines GIO <0: 1> may be aligned and output to the first input / output pad DQ0, and the third and fourth global lines GIO <2. (3) may be aligned and output to the second input / output pad DQ1.

On the other hand, most of the memory cell failure of the semiconductor memory device is a single bit failure, and in order to verify whether the single bit is defective, sequentially testing the single bits one by one is inadequate in terms of test time and test cost. Therefore, a need for a test circuit capable of checking whether a memory chip is defective within a short time has increased, and a circuit implemented by this need is a multi-bit parallel test circuit. The multi-bit parallel test circuit preferentially writes the same data to all the memory cells in the semiconductor memory device, and then reads the data stored in the memory cell at once and compares the read data, thereby detecting a failure when data having a different state is read. can do. In other words, instead of checking data output through a plurality of global lines through I / O pads, memory cell tests can be performed simply and quickly by checking compressed data output through some global lines through some I / O pads. have.

As discussed above, the memory cell failure can be relatively simply performed through the above test circuit. However, in order to ensure the reliability of the semiconductor memory device operation, it is necessary to verify not only the memory cell defect but also various parts of the data output path. For example, if there is a physical defect in a semiconductor manufacturing process on a global line, verification is also required. That is, various test circuits are required for increasing the reliability of semiconductor memory devices as well as memory cell tests.

The present invention provides a test circuit and a test method of a semiconductor memory device capable of confirming whether a data output path is defective.

The test circuit of the semiconductor memory device according to an embodiment of the present invention generates compressed data by comparing and compressing data stored in a plurality of memory cells in a memory bank in a first test mode, and selecting the compressed data as test data. Outputting to the input / output pad through one global line, transmitting the compressed data to a plurality of global lines in the second test mode, combining the respective compressed data on the plurality of global lines, and outputting the combination result. The test data is output to the input / output pad.

In an exemplary embodiment, a test circuit of a semiconductor memory device may include a memory bank configured to store data in a plurality of memory cells and to transmit the data to a plurality of global lines during a normal operation; A compression unit configured to generate compressed data by comparing and compressing data stored in the memory bank when the activated parallel test mode signal is applied and transmitting the compressed data to any one selected global line; A switch unit for transmitting the compressed data to at least one global line of the unselected global lines when the activated global line test mode signal is applied; And when the deactivated global line test mode signal is applied, output the data transmitted through the plurality of global lines or the compressed data transmitted through the one global line to an input / output pad, and activate the activated global line test. And a combination output unit for combining the compressed data carried on the plurality of global lines when the mode signal is applied, and outputting the combined result to the input / output pad as test data.

According to one or more exemplary embodiments, a method of testing a semiconductor memory device may include: collectively writing data applied to an input / output pad to a memory bank through a plurality of global lines when a write command is applied; When applying a read command, comparing and compressing data stored in the memory bank to generate compressed data, and transmitting the compressed data to a selected global line among the plurality of global lines; Outputting the compressed data transmitted to the selected global line as first test data to the input / output pad; Transmitting the compressed data to at least one global line of the selected global line and the unselected global line; Combining respective compressed data transmitted on the global line; And outputting the combined result as the second test data to the input / output pad.

According to the present technology, a reliable semiconductor memory device can be designed.

1 is a block diagram of a general semiconductor memory device;
2 is a block diagram illustrating a test circuit of a semiconductor memory device according to an embodiment of the present invention;
3 is a block diagram illustrating a test circuit of a semiconductor memory device according to an embodiment of the present invention;
4 is a block diagram illustrating a specific embodiment of the combined output unit of FIG. 3;
5 is a circuit diagram illustrating a specific embodiment of the combination of FIG. 4;
6 is a flowchart illustrating a test method of a semiconductor memory device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a test circuit of a semiconductor memory device according to an embodiment of the present invention. The test circuit of the illustrated semiconductor memory device is a circuit for performing the multi-bit parallel test discussed above.

In order to perform the multi-bit parallel test, first, the same data is collectively written to the memory bank through the input / output pad. Thereafter, during the read operation, by checking the level of the compressed data obtained by compressing the plurality of data stored in the memory cell, it is possible to confirm whether the memory cell is defective. 2 illustrates a configuration for implementing a read operation in a parallel test mode.

The semiconductor memory device of FIG. 2 includes a first bank 10, a second bank 20, and an output unit 50, and includes a first compression unit 30 and a second unit for performing parallel tests for each bank. Compression section 40 is included. Although an example of two memory banks has been described in the present embodiment, the test circuit may be applied to all semiconductor memory devices including at least one memory bank. Those skilled in the art will appreciate that the configuration and connection relationship between the memory bank and the compression unit may be variously designed as a concept of compressing multi-bit data to generate compressed data.

The first compression unit 30 and the second compression unit 40 operate by receiving the first test mode signal TM1. The first test mode signal TM1 is a signal that is activated when the parallel test mode is entered.

When the first test mode signal TM1 is activated, the first compression unit 30 receives data stored in a plurality of memory cells of the first bank 10, compares and compresses the first compressed data comp1. ) In detail, the first compression unit 30 generates activated first compressed data comp1 when the data stored in the first bank 10 are all at the same level. Techniques for compressing data during parallel testing are common, and are usually implemented using logic gates that output high levels when the data being compared are the same and low levels when they are different.

When the first test mode signal TM1 is activated, the second compression unit 40 receives data stored in a plurality of memory cells of the second bank 20, compares and compresses the second compressed data comp2. ) In detail, the second compression unit 40 generates the second compressed data comp2 that is activated when the data stored in the second bank 20 are all at the same level. The second compression unit 40 is also generally implemented using a logic gate that outputs a high level when the data being compared is the same and outputs a low level when the data to be compared are the same.

The first and second compressed data comp1 and 2 generated in the parallel test mode are loaded on the selected global line GIO <0: 1> for transmission to the output unit 50. That is, only some of the global lines GIO <0: 1> of the plurality of global lines GIO <0: 3> are driven. Accordingly, the output unit 50 arranges the compressed data comp1 and comp2 on the selected first and second global lines GIO <0: 1> and outputs the test data through the first input / output pad DQ0. do.

Therefore, according to the exemplary embodiment of the present invention, whether the memory cells of the first bank 10 and the second bank 20 are defective may be easily checked through the first input / output pad DQ0. However, since only some of the global lines GIO <0: 1> of the plurality of global lines GIO <0: 3> are driven during the test, the remaining global lines GIO <2: 3> operate normally. You can not check whether or not. If there is a physical defect in the manufacturing process on the global line, this causes a malfunction of the entire semiconductor memory device in the data input / output operation. Therefore, there is a need for a test circuit for checking whether a global line is defective.

3 is a block diagram illustrating a test circuit of a semiconductor memory device according to an embodiment of the present invention. The test circuit of the illustrated semiconductor memory device may perform the multi-bit parallel test described above, and perform a test for checking whether a global line is defective.

The test circuit of the semiconductor memory device of FIG. 3 includes the first and second banks 10 and 20, the first and second compression units 30 and 40, the first and second switch units 60 and 70, and the combined output. And part 80. Although an example of two memory banks has been described in the present embodiment, the test circuit may be applied to all semiconductor memory devices including at least one memory bank.

The connection and operation of the first bank 10, the first compression unit 30, the second bank 20, and the second compression unit 40 have been discussed above. Those skilled in the art will appreciate that the configuration and connection relationship between the memory bank and the compression unit may be variously designed as a concept of compressing multi-bit data to generate compressed data. In this case, the first compression unit 30 and the second compression unit 40 may further include a latch for latching and outputting the compressed data comp1 and comp2 during the test mode (at least the second test mode). The value must be maintained until the point at which the signal TM2 is activated. That is, it should be possible to maintain the compressed data (comp1, comp2) value until the parallel test is finished and the global line test is performed.

The first switch unit 60 and the second switch unit 70 operate by receiving the second test mode signal TM2. The second test mode signal TM2 is a signal that is activated when entering the global line test mode. In this case, the second test mode signal TM2 is activated after a predetermined time elapses after the first test mode signal TM1 is activated. That is, after the multi-bit parallel test is performed to output the compressed data comp1 and comp2 through the input / output pad DQ0, the device enters the global line test mode and tests whether the global line is defective.

When the second test mode signal TM2 is applied, the first switch 60 also transmits the first compressed data comp1 to the third global line GIO <2>. Although FIG. 3 illustrates the third global line GIO <2> as an example, the first compressed data comp1 may be transmitted to at least one or more global lines among the unselected global lines.

When the second test mode signal TM2 is applied, the second switch 70 also transmits the second compressed data comp2 to the fourth global line GIO <4>. Although FIG. 3 illustrates the fourth global line GIO <4> as an example, the second compressed data comp2 may be transmitted to at least one global line among unselected global lines.

The combined output unit 80 sorts the data or test data on the global lines GIO <0: 3> according to whether the second test mode signal TM2 is activated, and input / output pads DQ <0: 1>) or a combination of the test data loaded on the global lines GIO <0: 3> and output the combined result to a part of the input / output pads DQ <0: 1>.

4 is a block diagram illustrating a specific embodiment of the combined output unit 80.

The combined output unit 80 includes a selector 81, an output unit 83, and a combination unit 85.

The selector 81 controls the connection of the global lines GIO <0: 3> in response to the second test mode signal TM2. If the second test mode signal TM2 is in an inactive state, the global line GIO <0: 3> is connected to the output unit 83, and if the second test mode signal TM2 is in an active state, The global line GIO <0: 3> is connected to the combination unit 85. The selector 81 may be implemented by, for example, a switch.

The output unit 83 arranges the data or the compressed data comp1 and comp2 transmitted through the global lines GIO <0: 3> like the general output unit (shown in FIGS. 1 and 2) described above. Output to the input / output pads DQ <0: 1>.

On the other hand, the combination unit 85 combines the compressed data (comp1, comp2) of the global line carrying the same compressed data (comp1, comp2) in the global line test mode, and uses the combination result as a test data to input some input and output pad (DQ0) Output through

5 is a circuit diagram showing a specific embodiment of the combination unit 85.

The combiner 85 includes a first AND combiner 85_1, a second AND combiner 85_3, and a combination result output unit 85_5.

The first AND combiner 85_1 outputs a first combination result comb1 obtained by AND combining the first compressed data comp1 included in the first and third global lines GIO <0,2>. In detail, the first AND combining unit 85_1 may include a first NAND gate ND1 for receiving the plurality of first compressed data comp1 and a first inverter for inverting the outputs of the first NAND gate ND1 ( IV1). Therefore, when each of the first compressed data comp1 on the first and third global lines GIO <0,2> is the activated level, the first combination result comb1 of the activated level is determined. Output On the other hand, the first compressed data comp1 has an activated level or a low level first combination result comb1 when a defect occurs in any one of the global lines GIO <0,2>.

The second AND combiner 85_3 outputs a second combination result comb2 obtained by AND combining the second compressed data comp2 included in the second and fourth global lines GIO <1,3>. In detail, the second AND combining unit 85_3 may include a second inverter NND for receiving a plurality of the second compressed data comp2 and a second inverter for inverting the outputs of the second NAND gate ND2 ( IV2). Therefore, when each of the second compressed data comp2 on the second and fourth global lines GIO <1,3> is the activated level, the second combination result comb2 of the activated level is determined. Output On the other hand, the second compressed data comp2 is at an activated level, or when a defect occurs in any one of the global lines GIO <1,3>, a second combination result comb2 having a low level is output.

The combination result output unit 85_5 receives the first and second combination results comb1 and comb2, sorts them, and outputs the first and second combination results comb1 and comb2 to the first input / output pad DQ0 as test data. The specific configuration and operation of the combination result output unit 85_5 is the same as the general output unit 50 discussed above.

As described above, the test circuit of the semiconductor memory device according to the exemplary embodiment of the present invention may check the memory cell failure through the first test data output during the multi-bit parallel test. Then, the second test data output during the global line test may be compared with the first test data to determine whether the global line is defective. If the second test data is output at the deactivated level even though the first test data is output at the activated level, it can be seen that the global line is defective.

That is, the test circuit of the semiconductor memory device according to the embodiment of the present invention may perform a multi-bit parallel test to check memory cell failure through compressed data, and then transmit the compressed data to a plurality of global lines. By confirming the result of combining the data on the global line, it is possible to confirm whether the global line is defective.

6 is a flowchart illustrating a test method of a semiconductor memory device according to an embodiment of the present invention.

Specific test method is as follows.

First, in order to perform a multi-bit parallel test on the semiconductor memory device, the first test mode signal TM1 is activated to a high level (S1). Thereafter, when the write command WRITE activated at the high level is applied (S2), the data applied to the input / output pads are collectively written to the plurality of memory cells in the memory bank through the global line (S3).

After the write operation is finished, when a read command READ activated at a high level is applied (S4), the plurality of data stored in the memory bank are compared and compressed to generate compressed data, and the compressed data is selected as a global line. The controller transmits the data to the input / output pad (S5). In this case, the compressed data is activated when the plurality of data stored in the memory bank are all at the same level, and the compressed data is inactivated when any one of the plurality of data stored in the memory bank is at a different level. Whether the memory cell is defective may be determined based on the compressed data output through the input / output pad.

If the second test mode signal TM2 is activated to a high level after a predetermined time (S6), the compressed data is also transmitted to at least one or more global lines of the unselected global lines (S7). The combination data of each of the compressed data on the plurality of global lines is combined to output a combination result through an input / output pad. In this case, when each of the compressed data on the plurality of global lines is an activated level, the combination result of the activated level is output. On the other hand, the compressed data outputs the combined result of the deactivated level or the deactivated result when a defect occurs in any one of the global lines.

That is, the memory cell failure and the defect of the global line can be detected by outputting the compressed data and the combination result and comparing the combination data by the test method of the semiconductor memory device according to the exemplary embodiment of the present invention.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: first bank 20: second bank
30: first compression unit 40: second compression unit
50: output unit 60: first switch unit
70 second switch portion 80 combination output portion

Claims (12)

In the first test mode, compressed data is generated by comparing and compressing data stored in a plurality of memory cells in a memory bank, and outputting the compressed data to an input / output pad through one global line selected as test data,
In the second test mode, the semiconductor memory device which transmits the compressed data to a plurality of global lines, combines each of the compressed data loaded on the plurality of global lines, and outputs the combined result as the test data to the input / output pad. Test circuit. The method of claim 1,
A test circuit of the semiconductor memory device to generate the compressed data when the data stored in the plurality of memory cells in the memory bank are all at the same level. The method of claim 1,
And in the second test mode, outputting the combination result of the activated level when each of the compressed data contained in the plurality of global lines is the activated level. A memory bank for storing data in a plurality of memory cells and transferring the data to a plurality of global lines during a normal operation;
A compression unit configured to generate compressed data by comparing and compressing data stored in the memory bank when the activated parallel test mode signal is applied and transmitting the compressed data to any one selected global line;
A switch unit for transmitting the compressed data to at least one global line of the unselected global lines when the activated global line test mode signal is applied; And
When the deactivated global line test mode signal is applied, the data transmitted through the plurality of global lines or the compressed data transmitted through the one global line is output to an input / output pad, and the activated global line test mode is activated. And a combined output unit for combining the compressed data carried on the plurality of global lines and outputting the combined result to the input / output pad as test data when a signal is applied. 5. The method of claim 4,
And the global line test mode signal is activated after a predetermined time has passed since the parallel test mode signal is activated. 5. The method of claim 4,
Wherein the compression unit comprises:
A test circuit of the semiconductor memory device to generate the compressed data when the data stored in the memory bank are all at the same level. 5. The method of claim 4,
The combined output unit,
A selection unit connecting the plurality of global lines to an output unit when the global line test mode signal is in an inactive state and connecting the plurality of global lines to a combination unit when the global line test mode signal is in an active state;
An output unit for sorting the data transmitted through the plurality of global lines or the compressed data transmitted through the partial global lines and outputting the compressed data to the input / output pads; And
And a combiner for combining the compressed data on the plurality of global lines and outputting the combined result as the test data to the input / output pad. The method of claim 7, wherein
The combination part,
And outputting the combination result of the activated levels when each of the compressed data on the plurality of global lines is an activated level. The method of claim 7, wherein
The combination part,
And an AND gate which receives the compressed data on the plurality of global lines and generates the combination result. Writing the data applied to the input / output pads to the memory bank collectively through a plurality of global lines when the write command is applied;
When applying a read command, comparing and compressing data stored in the memory bank to generate compressed data, and transmitting the compressed data to a selected global line among the plurality of global lines;
Outputting the compressed data transmitted to the selected global line as first test data to the input / output pad;
Transmitting the compressed data to at least one global line of the selected global line and the unselected global line;
Combining respective compressed data transmitted on the global line; And
And outputting the result of the combination as the second test data to the input / output pad. 11. The method of claim 10,
And generating compressed data by comparing and compressing data stored in the memory bank to generate compressed data when the data stored in the memory bank are all at the same level. 11. The method of claim 10,
And combining the compressed data transmitted to the global line and outputting the combined result of the activated level when each of the compressed data loaded on the global line is the activated level.

Images