KR20120080352A - Semiconductor memory apparatus, check circuit for parallel test therefor - Google Patents

Semiconductor memory apparatus, check circuit for parallel test therefor Download PDF

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KR20120080352A
KR20120080352A KR1020110001753A KR20110001753A KR20120080352A KR 20120080352 A KR20120080352 A KR 20120080352A KR 1020110001753 A KR1020110001753 A KR 1020110001753A KR 20110001753 A KR20110001753 A KR 20110001753A KR 20120080352 A KR20120080352 A KR 20120080352A
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South Korea
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input
data
output
parallel test
write
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KR1020110001753A
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Korean (ko)
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윤순혁
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에스케이하이닉스 주식회사
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Publication of KR20120080352A publication Critical patent/KR20120080352A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: A semiconductor memory device and a parallel test verifying circuit therefor are provided to improve the reliability of a parallel test result in a memory cell by verifying a write data logic and a read data logic before a parallel test is performed. CONSTITUTION: A write driver/sense amplifier unit(120) writes data in a memory cell array or reads the data from the memory cell array. An input and output pad unit(130) inputs the data to the write driver and outputs the data from the sense amplifier unit. A parallel test verifying circuit(140) includes a plurality of registers, stores the data transmitted from the input and output pad unit in response to a parallel test verifying mode enable signal and outputs the data stored in the register to the input and output pad unit.

Description

Semiconductor Memory Apparatus and Parallel Test Verification Circuit for It {Semiconductor Memory Apparatus, Check Circuit for Parallel Test Therefor}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory device and a parallel test verification circuit therefor.

Memory devices such as DRAM and PCRAM should be tested to verify their normal operation after manufacturing is complete. In addition, it is common to perform a parallel test (TPARA mode) in order to reduce the time required for the test. Through parallel testing, compressed data can be written to and read from the memory cell to verify that the memory cell is operating normally.

The parallel test process is described in detail as follows.

In the parallel test mode, for example, when performing a 4-bit compression test, data is input to four input / output lines through one input pad to write data to a memory cell. That is, data is input to the first to fourth input / output lines IO0 to IO3 through the first input pad DQ0, and fifth to eighth input / output lines IO4 to 8 through the second input pad DQ1. Input data into the ninth through twelfth input / output lines IO8 through IO11 through the third input pad, and into the thirteenth through sixteenth input / output lines IO12 through IO15 through the fourth input pad. Write test data to the cell. Then, the data output through the four input and output lines are compared and compressed into one and output through the output pad.

If the data output through the four I / O lines are the same, the logic high (H) level data is output through the output pad. If any one of the data is different, the logic low (L) level data is output. Can be output through the pad.

As described above, compressed data is transmitted to four input / output lines and written to a memory cell, and data output from the memory cell is compressed into four input / output line units to output a comparison result. Therefore, the test can be performed using a small number of input / output pads, and the test can be performed on several dies at the same time, thereby reducing the time required for the test.

However, when the parallel test is performed in the initial state where the memory cell is not stabilized, the test result may be unreliable. Therefore, the reliability of the test logic must first be determined before performing the parallel test. To do this, data must be written to the memory cell to verify the parallel test logic, which requires a considerable time.

Furthermore, when data is not written to a memory cell due to a core environment problem or a write condition problem when verifying the parallel test logic, the reliability of the parallel test logic cannot be verified, and thus initial response is difficult.

SUMMARY The present invention provides a semiconductor memory device capable of easily verifying reliability of parallel test logic and a parallel test verification circuit for the same.

Another object of the present invention is to provide a semiconductor memory device capable of quickly coping with an initial failure during a parallel test process, and a parallel test verification circuit therefor.

According to one or more exemplary embodiments, a semiconductor memory device may include a write driver / sense amplifier unit writing data into a memory cell array or reading data from the memory cell array; An input / output pad unit for inputting data to the write driver or receiving data from the sense amplifier unit and outputting the data; And a plurality of registers connected between the write driver / sense amplifier unit and the input / output pad unit, and storing data transmitted from the input / output pad unit in response to the parallel test verify mode enable signal. And a parallel test verification circuit configured to output data stored in the register to the input / output pad unit.

On the other hand, the parallel test verification circuit according to an embodiment of the present invention is connected to each of the plurality of input and output pads, a plurality of input and output write multiplexer for receiving the data of the input and output pads in response to the parallel test verification mode enable signal; A plurality of registers respectively connected to the plurality of input / output write multiplexers to respectively store data transmitted from the input / output write multiplexer in response to the parallel test verify mode enable signal; And a plurality of input / output read multiplexers connected to the plurality of registers to receive the data of the registers and transmit the data of the registers to the input / output pads in response to the parallel test verification mode enable signal.

In the present invention, the compressed data is written and read in a register before performing the parallel test, and the data stored in the register is compressed and read to verify the parallel test logic.

Therefore, if a problem exists in the test logic, it is solved at the early stage, so that more accurate parallel test can be performed.

1 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention;
2 is a view for explaining a parallel test verification circuit according to an embodiment of the present invention;
3 is a view for explaining a light check method using the parallel test verification circuit shown in FIG.
4 is a diagram for describing a read check method using the parallel test verification circuit illustrated in FIG. 2.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

1 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

As shown, the semiconductor memory device 10 according to an embodiment of the present invention is a memory cell array 110 including a plurality of memory cells arranged between a word line (not shown) and a bit line (not shown), A write driver and a sense amplifier (WD / SA) 120 for writing data to or reading data from the selected memory cell of the memory cell array 110, and providing data to be written to the memory cell to the write driver WD. Or an input / output pad unit 130 including a plurality of input / output pads DQ0 to DQ3 for outputting data read by the sense amplifier SA.

In addition, the apparatus further includes a parallel test verification circuit 140 connected between the input / output pad unit 130 and the write driver / sense amplifier 120. The parallel test verification circuit 140 includes a plurality of registers and operates in response to the parallel test verification mode enable signals TPARAWC and TPARARC before the actual parallel test is performed. In the write check mode of the parallel test verification mode, compressed data is received from one of the input / output pads constituting the input / output pad unit 130 and stored in the registers, and the data stored in the register is output through the respective input / output pads. .

In addition, in the read check mode of the parallel test verification mode, data is received from each input / output pad constituting the input / output pad unit 130 and stored in a register, and the data read from the register is compressed into one data to input / output pad unit. Outputs through any one of the input and output pads constituting (130).

That is, before performing the parallel test on the memory cell array 110, the parallel test logic is verified by writing and reading the parallel test data to a register provided in the parallel test verification circuit 140. .

2 is a diagram illustrating a parallel test verification circuit according to an embodiment of the present invention.

Referring to FIG. 2, the parallel test verification circuit 140 includes a plurality of IO write multiplexers 1421, 1423, 1425, and 1427 and input / output pads DQ0 respectively connected to the input / output pads DQ0, DQ1, DQ2, and DQ3. IO lead multiplexers (1431, 1433, 1435, 1437), IO write multiplexers (1421, 1423, 1425, 1427) connected to the DQ1, DQ2, and DQ3, respectively. 1433, 1435, 1437 and a plurality of registers 1441, 1443, 1445, and 1447 connected between the write driver / sense amplifier unit 120, respectively.

In the present invention, the parallel test verification mode may be defined as a mode for determining the reliability of the parallel test logic executed before the parallel test.

The parallel test verification circuit 140 stores the data transmitted from the input / output pad in the first register in the parallel test verification mode and reads it again to check whether there is an error.

In order to perform the parallel test verify mode at high speed, the parallel test verify mode may also be performed in the compressed mode. To this end, the parallel test verification circuit 140 may further include a first compression unit 1410 and a second compression unit 1450.

The first compression unit 1410 may be connected to each input / output pad group including an input / output pad group corresponding to a predetermined compression unit, and may be connected between a specific input / output pad of the corresponding input / output pad group and each IO write multiplexer. . The second compression unit 1450 may also be connected to each IO lead multiplexer group including an IO lead multiplexer corresponding to a predetermined compression unit, and may be connected to a specific IO lead multiplexer of the IO lead multiplexer group. Is connected between the register and each register.

1 illustrates an example in which the compression unit is four. In this case, one input / output pad group includes four input / output pads DQ0 to DQ3, and one IO lead multiplexer group includes four IO lead multiplexers 1431, 1433, 1435, and 1437. . The first compression unit is connected between the first input / output pad DQ0 and the first to fourth IO write multiplexers 1421, 1423, 1425, and 1427, and the second compression unit 1450 is connected to the first IO lead multi. It can be seen that the flexure 1431 is connected between the first to fourth registers 1441, 1443, 1445, and 1447.

The operation in the write check mode when the parallel test verification mode is performed by the 4-bit compression unit is as follows.

The write check mode is performed by recording the same data for each preset compression unit and reading the same data through each input / output pad. At this time, the parallel test verification write check enable signal TPARAWC is enabled so that the first to fourth IO write multiplexers 1421, 1423, 1425, and 1427 and the first to fourth registers 1445, 1443, and 1445. 1447) is enabled. In addition, the parallel test verification read check enable signal TPARARC is disabled so that the first to fourth IO read multiplexers 1431, 1433, 1435, and 1437 operate in the normal mode.

When the parallel test verification write check enable signal TPARAWC is enabled, the first to fourth IO write multiplexers 1421, 1423, 1425, and 1427 transmit the write input / output lines DQ0 to DQ3. The signals of the WIO0 to WIO3 are ignored and the data output from the first compression unit 1410 is received. Therefore, the data input through the first input / output pad DQ0 is transmitted to the first to fourth IO write multiplexers 1421, 1423, 1425, and 1427 through the first compression unit 1410, and then, respectively. The first through fourth registers 1441, 1443, 1445, and 1447 are stored.

Subsequently, when the read operation is performed, the data of the first through fourth registers 1441, 1443, 1445, and 1447, not the data of the sense amplifier SA, are transmitted through the global read input / output lines RGIO0 to RGIO3. 4th IO read multiplexers 1431, 1433, 1435, 1437, respectively. Since the parallel test verification read check enable signal TPARARC is disabled, the first to fourth IO read multiplexers 1431, 1433, 1435, and 1437 disable the read input / output lines RIO0 to RIO3 and the data transmission path. Set to output data to each input / output pad DQ0 to DQ3.

Thus, the reliability of the write data logic of the parallel test can be determined by comparing the logic level of the output data with the logic level of the input data.

In the read check mode of the parallel test verification mode, the parallel test verification circuit 140 operates as follows.

At this time, the parallel test verify write check enable signal TPARAWC is disabled, and the parallel test verify read check enable signal TPARARC is enabled.

Accordingly, the first to fourth IO write multiplexers 1421, 1423, 1425, and 1427 receive data of the input / output pads DQ0 to DQ3 through the write input / output lines WIIO0 to WIO3 connected to the first to fourth IO write multiplexers 1421, 1423, 1425, and 1427. The data of the IO write multiplexers 1421, 1423, 1425, and 1427 are stored in the registers 1441, 1443, 1445, and 1447 through the global write I / O lines WGIO0 to WGIO3.

At this time, since the parallel test verification read check enable signal TPARARC is enabled, when the read command is input, the output data of the first to fourth registers 1441, 1443, 1445, and 1447 is output to the second compression unit 1450. Is transmitted to the first IO read multiplexer 1431 through. The data of the first IO read multiplexer 1431 is output through the first input / output pad DQ0.

Therefore, the reliability of the parallel test read data logic can be determined by comparing the level of the input data with the logic level of the data output from the first input / output pad DQ0.

That is, when the write check is performed in the parallel test verification mode, the number of IO write multiplexers 1421, 1423, 1425, and 1427 corresponding to one input / output pad and a compression unit are transmitted by the first compression unit 1410. After the same data is written to a plurality of registers by setting, the data stored in each register is read through each input / output pad.

In addition, during read checking in the parallel test verification mode, data of a predetermined level is written into a register. The second compression unit 1450 sets a data transmission path between the registers 1441, 1443, 1445, and 1447 corresponding to the compression unit and one IO read multiplexer 1431, and transmits data. The data of the routed IO read multiplexer 1431 is read through the input / output pad.

Therefore, by verifying the parallel test logic first before performing the parallel test of writing and reading test data directly into the memory cell, it is possible to improve the reliability of the test result for the actual memory cell. In addition, if the reliability of the parallel test logic is not satisfied, the logic can be modified immediately, thereby improving test efficiency.

FIG. 3 is a diagram for describing a light check method using the parallel test verification circuit shown in FIG. 2.

For example, it is assumed that the verification is performed in the 4-bit compression unit in the write check mode of the parallel test verification. The first to fourth input / output pads DQ0 to DQ3, the fifth to eighth input / output pads DQ4 to DQ7, the ninth to twelfth input / output pads DQ8 to DQ11, and the thirteenth to sixteenth input / output pads DQ12. DQ15 is set to the unit input / output pad group, and the logic high level H, the second group DQ4 to DQ7, and the fourth group for the first group DQ0 to DQ3 and the third group DQ8 to DQ11. For (DQ12 to DQ15), data of logic low (L) level is input.

After the parallel test verification write check enable signal TPARAWC is enabled and the parallel test verification read check enable signal TPARARC is disabled, the I / O pads of the first group DQ0 to DQ3 are responded to in response to the write command. Data of logic high level (H) is input through.

Then, the first to fourth IO write multiplexers 1421, 1423, 1425, and 1427 form a data transmission path with the first input / output pad DQ0 through the first compression unit 1410, and have a logic high level. Data is sent to the first through fourth IO write multiplexers 1421, 1423, 1425, 1427. The data of the first to fourth IO write multiplexers 1421, 1423, 1425, and 1427 are transmitted to the first to fourth registers 1441, 1443, 1445, and 1447 through the global write I / O lines WGIO0 to WGIO3. Are stored in.

Subsequently, when a read command is input, the data of the first to fourth registers 1441, 1443, 1445, and 1447 is transmitted to the first to fourth IO read multiplexers 1431 through the global read I / O lines RGIO0 to RGIO3. 1433, 1435, and 1437, and then are output through the respective I / O pads DQ0 to DQ3 through the respective read I / O lines RIO0 to RIO3.

Since the logic high level data is input through the first input / output pad DQ0 during the write operation, all data output from the first to fourth input / output pads DQ0 to DQ3 in response to the read command may be at the high level. In this case, it may be determined that the write data logic is reliable.

Reliability of the write data logic can be determined by writing and reading the data in the same operations as in the first group also in the second to fourth groups.

4 is a diagram for describing a read check method using the parallel test verification circuit illustrated in FIG. 2.

In the present exemplary embodiment, the read check mode is performed in a 4-bit compression unit, and high / low / high / low (HLHL) data is included in the input / output pads DQ0 to DQ3 included in the first group. Data of high / high / high / high (HHHH) is included in the input / output pads (DQ4 to DQ7), and data of low / high / low / high (LHLH) is included in the input / output pads (DQ8 to DQ11) included in the third group. Low / low / low / low (LLLL) data is recorded in the input / output pads DQ12 to DQ15 included in the fourth group.

Referring to the first group as an example, after the parallel test verify read check enable signal TPARARC is enabled and the parallel test verify write check enable signal TPARAWC is disabled, the first group is responsive to the write command. Input data of high, low and high low level through input / output pads of (DQ0 ~ DQ3) respectively.

Data input through the input / output pads DQ0 to DQ3 is transmitted to the first to fourth IO write multiplexers 1421, 1423, 1425, and 1427 through respective write input / output lines WIO0 to WIO3, and then global. The first to fourth registers 1441, 1443, 1445, and 1447 are stored through the write input / output lines WGIO0 to WGIO3.

Thereafter, when a read command is input, data of the first to fourth registers 1441, 1443, 1445, and 1447 is transmitted to the first IO read multiplexer 1431 through the second compression unit 1450. It is transmitted through the first input / output pad DQ0.

The second compression unit 1450 may be configured to output high level data when the logic levels of the input data are the same, and output low level data when the logic levels of the input data are not all the same. .

Since the data of the high / low / high / low level is recorded for the first group during the write operation, when the data is correctly recorded in the first register, the second compression unit 1450 outputs the low level data.

The read check may be performed in the same manner with respect to the second to fourth groups.

As described above, in the present invention, the verification of the parallel test logic is first performed before the parallel test is performed on the memory cell. To this end, the parallel test verification circuit 140 includes a register, and writes and reads data input through the input / output pads to the register, and compares the parallel test logic by comparing the logic level of the read data with the data provided for writing. To determine the reliability of.]

Furthermore, the compression test can be applied in the parallel test verification mode. In this case, at the time of a write check, one data is stored in a plurality of registers and then read through each input / output pad. In addition, during read checking, data input through each input / output pad is stored in each register, and the data stored in each register is compressed and output.

Therefore, the write data logic and the read data logic can be verified before performing the actual parallel test, so that the initial failure can be immediately responded to, and the reliability of the result of performing the parallel test on the memory cell can be improved.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: semiconductor memory device
110: memory cell array
120: light driver / sense amplifier
130: input and output pad unit
140: parallel test verification circuit

Claims (9)

A write driver / sense amplifier unit for writing data to or reading data from the memory cell array;
An input / output pad unit for inputting data to the write driver or receiving data from the sense amplifier unit and outputting the data; And
A data connected between the write driver / sense amplifier section and the input / output pad section and including a plurality of registers, in response to a parallel test verification mode enable signal, storing data transmitted from the input / output pad section in the register, A parallel test verification circuit for outputting data stored in the register to the input / output pad unit;
And a semiconductor memory device. The method of claim 1,
The input / output pad unit includes a plurality of input / output pads,
The parallel test verification circuit may include an input / output write multiplexer connected between the input / output pad and the register to transmit data of the input / output pad to the register in response to the parallel test verification mode enable signal; And
An input / output read multiplexer connected between the input / output pad and the register to transmit data of the register to the input / output pad in response to the parallel test verify mode enable signal;
And a semiconductor memory device. The method of claim 2,
The parallel test verification circuit further includes a first compression unit connected between any one of the plurality of input / output pads and a specified number of the input / output write multiplexers,
And the first compression unit transmits data of an input / output pad to which the first compression unit is connected to the specified number of input / output write multiplexers in response to the parallel test verify mode enable signal. The method of claim 3, wherein
The parallel test verification circuit further includes a second compression unit connected between a specified number of registers and a plurality of the input / output read multiplexers,
And the second compression unit compresses data output from the specified number of registers in response to the parallel test verify mode enable signal and transmits the data output to the input / output read multiplexer to which the second compression unit is connected. A plurality of input / output write multiplexers respectively connected to the plurality of input / output pads and configured to receive data of the input / output pads in response to the parallel test verification mode enable signal;
A plurality of registers respectively connected to the plurality of input / output write multiplexers to respectively store data transmitted from the input / output write multiplexer in response to the parallel test verify mode enable signal; And
A plurality of input / output read multiplexers connected to the plurality of registers to receive the data of the registers and transmit the received data to the input / output pads in response to the parallel test verify mode enable signal;
Parallel test verification circuit comprising a. The method of claim 5, wherein
A connection between any one of the plurality of input / output pads and a specified number of input / output write multiplexers to provide data of the input / output pads to the specified number of input / output write multiplexers in response to the parallel test verify mode enable signal. Parallel test verification circuit further comprising a first compression unit. The method of claim 5, wherein
A second compression unit connected between a specified number of registers and any one of the plurality of input / output read multiplexers and compressing data of the registers to provide the input / output read bit in response to the parallel test verify mode enable signal; Parallel test verification circuit further comprising. The method of claim 7, wherein
And the second compression unit outputs data of a designated first logic level when all logic levels of input data are the same. The method of claim 8,
And the second compression unit outputs data of a specified second logic level when the logic levels of the input data are different.
KR1020110001753A 2011-01-07 2011-01-07 Semiconductor memory apparatus, check circuit for parallel test therefor KR20120080352A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170083173A (en) * 2016-01-07 2017-07-18 에스케이하이닉스 주식회사 Semiconductor Memory Apparatus
US11967389B2 (en) 2022-01-03 2024-04-23 SK Hynix Inc. Semiconductor apparatus related to a test function

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170083173A (en) * 2016-01-07 2017-07-18 에스케이하이닉스 주식회사 Semiconductor Memory Apparatus
US11967389B2 (en) 2022-01-03 2024-04-23 SK Hynix Inc. Semiconductor apparatus related to a test function

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