KR20120042578A - Test circuit of semiconductor device - Google Patents

Test circuit of semiconductor device Download PDF

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Publication number
KR20120042578A
KR20120042578A KR1020100104316A KR20100104316A KR20120042578A KR 20120042578 A KR20120042578 A KR 20120042578A KR 1020100104316 A KR1020100104316 A KR 1020100104316A KR 20100104316 A KR20100104316 A KR 20100104316A KR 20120042578 A KR20120042578 A KR 20120042578A
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KR
South Korea
Prior art keywords
data
test
representative
output
input
Prior art date
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KR1020100104316A
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Korean (ko)
Inventor
백현권
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020100104316A priority Critical patent/KR20120042578A/en
Publication of KR20120042578A publication Critical patent/KR20120042578A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

Abstract

PURPOSE: A test circuit of a semiconductor device is provided to reduce package costs by preemptively detecting a defect of a global input/output line in a probe test. CONSTITUTION: A plurality of global input and output lines(210) are connected to a plurality of data pads. A plurality of write driving units drive data applied from the plurality of global input and output lines and outputs data to a bank. A plurality of input and output sense amplifiers sense and amplify data applied from the bank and outputs the data to the plurality of global input and output lines. A plurality of local input and output lines(400) are connected to the plurality of write driving units and the plurality of input and output sense amplifiers.

Description

Test circuit of semiconductor device

An embodiment of the present invention relates to a test circuit of a semiconductor device, and more particularly to a memory device capable of a data compression test.

Recently, semiconductor memory devices have a read global bus and a write global bus instead of one global bus to improve the slope of a global input / output signal.

The write global bus transfers data from the data pads into the cell array upon data writing. The read global bus then transfers data from the cell array towards the data pads upon data read.

In addition, with the development of process technology, as semiconductor memory devices are highly integrated, tests are performed for a long time with expensive test equipment after manufacturing to ensure chip reliability.

In order to test such a memory device, in order to reduce the time and cost of the test, a self test circuit is built in the chip in advance in the design stage.

In a conventional semiconductor memory device, a self test mode called a data compression test (DQ Compress Test) is used to reduce test time.

The DQ compress test, which is a kind of self-test, stores the same data in a plurality of memory cells and outputs the data again at the same time, and then compresses the outputted data at the same time, thereby testing whether there is an error in the memory. That's how.

When a compression test is performed in a semiconductor memory device, the same data is written to several input / output lines using one input / output line, and external data is input through the data (DQ) pad to latch the data (DQ). It is stored in a latch, and one I / O sense amplifier is connected to one data latch.

When performing the data compression test, the compressed data is output, thereby minimizing the number of used data output channels (ie, data pads). Thus, the data compression test enables testing of multiple dies at the same time.

1 is a block diagram of a test circuit of a semiconductor device according to the prior art.

The test circuit of the semiconductor device according to the related art includes a pad unit 10, a global input / output (GIO) line unit 20, 21, a compression test unit 30, 31, and a local input. And a local input / output (LIO) line portion 40 and banks B0 and B1.

Here, the pad unit 10 includes a plurality of data pads DQ0 to DQ7. The plurality of data pads DQ0 to DQ7 are connected to the global input / output line GIO, respectively.

The compression test units 30 and 31 are connected between the global input / output line unit 20 and the global input / output line unit 21 to compress the input / output data during the probe test. Will be performed.

The write driver WD and the input / output sense amplifier IOSA are connected between the global input / output line section 21 and the local input / output line section 40. Each write drive WD and input / output sense amplifier IOSA are connected to a local input / output line LIO.

Here, the write driver WD drives input data applied from the compression test units 30 and 31 and outputs them to the banks B0 and B1. The input / output sense amplifier IOSA senses and amplifies the output data applied from the banks B0 and B1 and outputs them to the compression test units 30 and 31.

In a semiconductor memory device such as a DRAM, an input / output data compression mode is used for a probe test. In the input / output data compression mode, only one representative data pad of the pads of the pad unit 10 is used. This reduces the test time and the cost in the input / output data compression mode.

For example, in FIG. 1, one data pad DQ0 of the four data pads DQ0 to DQ3 is used as the representative pad, and one data pad DQ4 of the four data pads DQ4 to DQ7 is used as the representative pad.

However, if a failure occurs in the global input / output line GIO connected to the remaining non-representative data pads DQ1 to DQ3 and DQ5 to DQ7 that are not used in the input / output data compression mode, there is no way to screen them.

The global input / output line GIO of the global input / output line unit 20 includes a second metal layer M2 and a third metal layer M3. However, when the second metal layer M2 and the third metal layer M3 are disconnected or the metal contact M3C is not opened, the global input / output line connected to the non-representative data pads DQ1 to DQ3 and DQ5 to DQ7. Defects occur in the GIO.

However, in the test circuit of the conventional semiconductor device, since the non-representative data pads DQ1 to DQ3 and DQ5 to DQ7 are not used in the input / output data compression mode, the test circuit cannot be screened even if a defect occurs.

In particular, subsequent package tests will use the input / output normal mode using all data pads DQ0 to DQ7 instead of the input / output data compression mode. At this time, a failure of the global input / output line GIO, which is not detected in the wafer level probe test, is detected in the package test step so that package failure occurs. If package failure occurs at the package stage, loss of package cost occurs.

An embodiment of the present invention is characterized in that a probe test screen can be performed by detecting a failure of a global input / output line of non-representative pads in an input / output data compression mode of a semiconductor memory device.

In addition, an embodiment of the present invention has a feature to reduce the package cost by detecting the failure of the global input / output line in advance during the probe test.

A test circuit of a semiconductor device according to an embodiment of the present invention includes a plurality of data pads for inputting / outputting data; A plurality of global input / output lines connected to the plurality of data pads; A plurality of write drivers for driving data applied from a plurality of global input / output lines and outputting them to a bank; A plurality of input / output sense amplifiers for sensing and amplifying data applied from a bank and outputting the data to a plurality of global input / output lines; A plurality of local input / output lines connected to the plurality of light drivers and the plurality of input / output sense amplifiers; And a plurality of test lines connected to the plurality of data pads and the plurality of global input / output lines to form a high voltage transfer path applied from a representative data pad among the plurality of data pads in the test mode.

An embodiment of the present invention enables a probe test screen to be performed by detecting a failure of a global input / output line of non-representative pads in an input / output data compression mode of a semiconductor memory device.

In addition, the embodiment of the present invention provides an effect of reducing the package cost by detecting the failure of the global input / output line in advance during the probe test.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1 is a block diagram of a test circuit of a conventional semiconductor device.
2 is a block diagram of a test circuit of a semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a test circuit of a semiconductor device according to an embodiment of the present invention.

Embodiments of the present invention include a pad unit 100, a global input / output (GIO) line unit 200 and 210, a compression test unit 300 and 310, and a local input / output (LIO). Output) line portion 400, and a plurality of switching elements SW1 ~ SW7 and banks B0, B1.

Here, the pad unit 100 includes a plurality of data pads DQ0 to DQ7. The plurality of data pads DQ0 to DQ7 are connected in one-to-one correspondence with the global input / output lines GIO0 to GIO7, respectively.

The global input / output line GIO0 connected to the representative data pad DQ0 among the plurality of data pads DQ0 to DQ3 is connected to the write driver WD and the input / output sense amplifier IOSA through the compression test unit 300. The global input / output lines GIO1 to GIO3 connected to the remaining non-representative data pads DQ1 to DQ3 are not connected to the compression test unit 300 but are directly connected to the corresponding write driver WD and input / output sense amplifier IOSA.

The global input / output line GIO4 connected to the representative data pad DQ4 among the plurality of data pads DQ4 to DQ7 is connected to the write driver WD and the input / output sense amplifier IOSA through the compression test unit 310. The global input / output lines GIO5 to GIO7 connected to the remaining non-representative data pads DQ5 to DQ7 are not connected to the compression test unit 310 but are directly connected to the corresponding write driver WD and input / output sense amplifier IOSA.

The compression test units 300 and 310 are connected between the global input / output line unit 200 and the global input / output line unit 210 to perform a compression mode of input / output data during a probe test. Done.

When performing the data compression test, the global input / output line unit 210 uses the compression test unit 300 to apply data applied from one global input / output line GIO0 included in the global input / output line unit 200. The same data is written to several global input / output lines included in (eg, four in FIG. 2).

In the data compression test, the data applied from one global input / output line GIO4 included in the global input / output line unit 200 is input to the global input / output line unit (using the compression test unit 310). The same data is written to several global input / output lines included in 210 (eg, four in FIG. 2).

For example, when data is input to the representative data pad DQ0, the data is input to the compression test unit 300 through the global input / output line GIO0. Then, the compression test unit 300 compresses the data and outputs the same data to all four write drivers WD connected to the bank B0.

The data delivered to the four write drivers WD is stored in bank B0 via the corresponding four local input / output lines LIO.

Eventually, only the representative data pad DQ0 is probed to transfer data to the compression test unit 300, and the local input / output line LIO of the local input / output line unit 400 connected to the non-representative data pads DQ1 to DQ3. Will store the data in bank B0.

Thereafter, the compression test units 300 and 310 code the data read from each input / output sense amplifier IOSA to determine a failure.

The write driver WD and the input / output sense amplifier IOSA are connected between the global input / output line unit 210 and the local input / output line unit 400. Each write drive WD and input / output sense amplifier IOSA are connected to a local input / output line LIO.

Here, the write driver WD drives input data applied from the compression test units 300 and 310 and outputs them to the banks B0 and B1. The input / output sense amplifier IOSA senses and amplifies the output data applied from the banks B0 and B1 and outputs them to the compression test units 300 and 310.

In a semiconductor memory device such as a DRAM, an input / output data compression mode is used for a probe test. In the input / output data compression mode, only one representative data pad of the pads of the pad unit 100 is used. This reduces the test time and the cost in the input / output data compression mode.

For example, one data pad DQ0 of the four data pads DQ0 to DQ3 is used as the representative pad, and one data pad DQ4 of the four data pads DQ4 to DQ7 is used as the representative pad.

In addition, in an embodiment of the present invention, a failure occurs in the global input / output lines GIO1 to GIO3 and GIO5 to GIO7 connected to the remaining non-representative data pads DQ1 to DQ3 and DQ5 to DQ7 that are not used in the input / output data compression mode. The plurality of test lines TL1 to TL7 for connecting the data pads DQ0 to DQ7, the write driver WD and the input / output sense amplifier IOSA, and the plurality of switching elements SW1 to control the connection state of the test lines TL1 to TL7. It allows you to screen it through SW7.

To this end, in the exemplary embodiment of the present invention, a plurality of test lines TL1 to a new path for screening failures of the global input / output lines GIO1 to GIO3 and GIO5 to GIO7 connected to the non-representative data pads DQ1 to DQ3 and DQ5 to DQ7 are provided. TL7 will be formed.

The paths of the plurality of test lines TL1 to TL7 are connected to the representative pad DQ4 starting from the representative data pad DQ0 and through the data pads DQ1, DQ2, DQ3, DQ7, DQ6, and DQ5.

That is, the paths of the plurality of test lines TL1 to TL7 start from the representative data pad DQ0, and then the data pad DQ1, the global input / output line GIO1, the data pad DQ2, the global input / output line GIO2, the data pad DQ3, the global input / output line It is connected to the representative pad DQ4 via GIO3, data pad DQ7, global input / output line GIO7, data pad DQ6, global input / output line GIO6, data pad DQ5, and global input / output line GIO5.

In this case, the global input / output lines GIO0 and GIO4 connected to the compression test units 300 and 310 do not correspond to the connection path in the test mode.

The test lines TL1 to TL7 each include a plurality of switching elements SW1 to SW7 for selectively connecting data pads. Here, the plurality of switching elements SW1 to SW7 preferably consist of NMOS transistors.

Each of the plurality of switching elements SW1 to SW7 is used to selectively connect lines on the plurality of test lines TL1 to TL7, and a control signal CON is applied through the gate terminal.

When the control signal CON is applied at a high level in the test mode, the plurality of switching elements SW1 to SW7 are turned on to connect the plurality of test lines TL1 to TL7 with each other. On the other hand, the plurality of switching devices SW1 to SW7 are turned off when the control signal CON is applied at the low level in the normal mode to cut off the connection between the plurality of test lines TL1 to TL7.

At this time, in the test mode, the control signal CON is applied at a level equal to or higher than the power supply voltage VDD and the threshold voltage Vtsat so that the plurality of switching devices SW1 to SW7 are turned on. Here, the power supply voltage VDD may be set to a level of about 1.5V, and the threshold voltage Vtsat of the transistor may be set to 0.7V.

On the other hand, in the normal mode, the control signal CON is applied at a level equal to or lower than the power supply voltage VDD + threshold voltage Vtsat so that the plurality of switching devices SW1 to SW7 maintain the turn-off state.

On the other hand, the test mode of the present invention is to screen the failure of the global input / output lines GIO1 ~ GIO3, GIO5 ~ GIO7 connected to the non-representative data pads DQ1 ~ DQ3, DQ5 ~ DQ7, the compression test unit (300,310) in the test mode Turn off).

The input high voltage VPPin is applied to the representative data pad DQ0, and a method of measuring the level of the output high voltage VPPout at another representative data pad DQ4 is used.

Here, the input high voltage VPPin may be set at the pumping voltage VPP level, and the pumping voltage VPP may be set at a voltage level of about 3V.

When the input high voltage VPPin is applied to the representative data pad DQ0 in the test mode of the present invention, the compression test units 300 and 310 are turned off and the pumping voltage VPP is transferred along the new test lines TL1 to TL7.

In the compression test operation as shown in FIG. 1 but not in the test mode according to the embodiment of the present invention, the level of the control signal CON becomes the ground voltage VSS or the core voltage VCORE level so that the plurality of switching devices SW1 to SW7 are turned on. Will remain off. Here, the ground voltage VSS may be set to 0V and the core voltage VCORE may be set to about 1 / 2V.

On the other hand, when the control signal CON becomes higher than the high voltage, that is, the power supply voltage VDD + threshold voltage Vtsat level in the test mode, the plurality of switching elements SW1 to SW7 are all turned on.

Then, the plurality of data pads DQ to DQ7, the write driver WD, the input / output sense amplifier IOSA, the global input / output lines GIO1 to GIO3, GIO7 to GIO5, and the plurality of test lines TL1 to TL7 are connected to each other to represent The input high voltage VPPin applied from the data pad DQ0 is output to the output high voltage VPPout through another representative data pad DQ4.

Accordingly, the high voltage VPPout output through the representative data pad DQ4 measures the level to test whether the global input / output line unit 200 is defective.

If the high voltage VPPout output through the representative data pad DQ4 is equal to the level of the input high voltage VPPin applied to the representative data pad DQ0, the global input / output line unit 200 is determined to be normal.

On the other hand, if the high voltage VPPout output through the representative data pad DQ4 is lower than the level of the input high voltage VPPin applied to the representative data pad DQ0, or if the output high voltage VPPout is not measured, the global input / output line unit 200 may fail. It is determined to have occurred.

That is, when a failure occurs in the global input / output line unit 200, the connection path of the test lines TL1 to TL7 is disconnected, so that the output high voltage VPPout level is not measured, and thus the fail state of the global input / output line GIO. Will be judged.

Claims (14)

A plurality of data pads for inputting / outputting data;
A plurality of global input / output lines connected to the plurality of data pads;
A plurality of write drivers configured to drive data applied from the plurality of global input / output lines and output them to a bank;
A plurality of input / output sense amplifiers for sensing and amplifying data applied from the bank and outputting the data to the plurality of global input / output lines;
A plurality of local input / output lines connected to the plurality of write drivers and the plurality of input / output sense amplifiers; And
And a plurality of test lines connected to the plurality of data pads and the plurality of global input / output lines to form a high voltage transfer path applied from a representative data pad among the plurality of data pads in a test mode. The test circuit of the semiconductor device. The method of claim 1, wherein the plurality of data pads are
A first representative data pad used in a compression test operation;
A plurality of first non-representative pads formed adjacent to the first representative data pad;
A second representative data pad used in the compression test operation; And
And a plurality of second non-representative pads formed adjacent to the second representative data pad. 3. The method of claim 2, wherein the first representative data pad and the plurality of first non-representative pads store data in a first bank, and the second representative data pad and the plurality of second non-representative pads are stored in a second bank. A test circuit for a semiconductor device, characterized by storing data. The method of claim 2, wherein the plurality of test lines
And a test line connecting one non-representative pad of the first representative data pad and the plurality of first non-representative pads. The method of claim 2, wherein the plurality of test lines
And a test line connecting the plurality of global input / output lines connected to the plurality of first non-representative pads to each other. The method of claim 2, wherein the plurality of test lines
And a test line connecting the global input / output lines connected to the plurality of first non-representative pads and the global input / output lines connected to the plurality of second non-representative pads. The method of claim 2, wherein the plurality of test lines
And a test line connecting the plurality of global input / output lines connected to the plurality of second non-representative pads to each other. The method of claim 2, wherein the plurality of test lines
And a test line connecting a global input / output line connected to one of the second representative data pads and one of the plurality of second representative pads. The test circuit of claim 2, wherein the high voltage applied from the first representative pad is detected through the second representative pad to determine whether the global input / output line is to be failed. 3. The method according to claim 1 or 2,
And a plurality of switching elements for selectively controlling the connections between the plurality of test lines. The method of claim 10, wherein each of the plurality of switching elements
And the control circuit is turned on by a control signal in the test mode. The test circuit of claim 11, wherein each of the plurality of switching elements is turned on when the control signal is applied at a voltage level equal to or greater than a power supply voltage level. The test circuit of claim 1, further comprising a compression test unit configured to compress data applied from the representative data pad and transmit the compressed data to the plurality of local input / output lines during a compression test operation. The test circuit of claim 13, wherein the compression test unit is turned off in the test mode.
KR1020100104316A 2010-10-25 2010-10-25 Test circuit of semiconductor device KR20120042578A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9423456B2 (en) 2013-07-05 2016-08-23 SK Hynix Inc. Parallel test device and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9423456B2 (en) 2013-07-05 2016-08-23 SK Hynix Inc. Parallel test device and method

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