KR20060031393A - Semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to fix test data of an input / output pad connected to an unselected bank in an input / output compression test mode for test reduction, thereby making it easy to create a test program and testing in a bank interleaved mode. This is a technique that reduces the test time if possible and when testing multiple chips. To this end, the present invention shares a global input / output line, a plurality of banks selected and driven by a plurality of bank address signals, and a plurality of normal mode input / output for amplifying data of a selected bank among the plurality of banks in a normal mode. Amplifying data of a selected bank among the plurality of banks in a sense amplifier and a test mode, and outputting a fixed output signal that is always passed when connected to an unselected bank among the plurality of banks according to the plurality of bank address signals; And a plurality of input / output sense amplifiers for outputting a test mode.

Description

Semiconductor memory device

1 is a block diagram of a conventional semiconductor memory device.

FIG. 2 is an internal circuit diagram of an input / output sense amplifier for the test mode of FIG. 1. FIG.

FIG. 3 is an input / output waveform diagram in normal mode of the semiconductor memory device of FIG. 1. FIG.

4 is an input / output waveform diagram in a test mode of the semiconductor memory device of FIG. 1.

5 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

6 is an internal circuit diagram of an input / output sense amplifier for the test mode of FIG.

7 is an input / output waveform diagram in a test mode of the semiconductor memory device of FIG. 5;

The present invention relates to a semiconductor memory device, and more particularly, by fixing read data of an input / output pad connected to an unselected bank in an input / output compression test mode for test reduction, a test in a bank interleaved mode is possible, This is a technique that reduces test time when testing.

In general, with the development of process technology, as semiconductor memory devices are highly integrated, in order to guarantee chip reliability, expensive test equipments are tested for a long time after manufacture.

Accordingly, with high integration of memory devices, test time accounts for a large portion of the cost of memory devices. Therefore, if the test time is efficiently reduced, the test cost can be reduced, thereby reducing the cost of the memory device.

In general, DRAM devices have a structure such as X4, X8, and X16. Here, X4, X8, and X16 mean how many data are output in one operation. If X16 to X8, the address is increased by one more, and to operate with X4, the address is increased by two more. In this state, the test time is doubled.

On the other hand, when testing wafers, instead of testing one chip at a time, eight or sixteen chips are tested simultaneously. In this case, as described above, to reduce the test time, the test should be performed with X16, which means that 16 DQ pins should exist for each chip. This not only increases the cost of the probe card for wafer testing, but can also pose significant difficulties in manufacturing.

An alternative to solve this problem is the DQ compress mode. DQ compression mode is a mode to operate X4 externally and X16 internally. That is, one data implies four data internally. This not only reduces test time, but also tests a single chip with only four data pins.

In addition, one of the advantages of the DQ compression mode is that it reduces the memory size of the test equipment. For example, if you apply a test equipment that can test 64M to 256M, it is not possible because of the small memory size.However, if you use DQ compression mode, you can test with 256/4 memory size. Is possible.

1 is a configuration diagram of a semiconductor memory device implementing a conventional deque compression mode.

The semiconductor memory device of FIG. 1 includes four banks 1, a plurality of normal mode input / output sense amplifiers 11, a test mode input / output sense amplifier 12, and a plurality of write drivers 13. The global input / output line shares a global input output (GIO).

The semiconductor memory device having the above structure compresses all input / output data of each bank in the test mode, activates one global input / output line GIO, and inputs and outputs data. That is, as shown in FIG. 1, in case of four banks, 16 data are compressed and output by four by using four global input / output line GIOs. Thus, activating each bank simultaneously compresses all data in each bank, reducing test time to one-quarter without the need for additional address pins.

FIG. 2 is an internal circuit diagram of the input / output sense amplifier 12 for the test mode of FIG. 1.

The input / output sense amplifier 11 for test mode includes inverters IV1 to IV3, NAND gates ND1, ND2, and NOR gate NOR1, PMOS transistor PM1, and NMOS transistor NM1.

The inverter IV1 inverts the write signal WTS, the NAND gate ND1 performs a NAND operation of the write signal WTS and the control signal TPARA, and the inverter IV2 inverts the output of the NAND gate ND1. The inverter IV3 inverts the output of the inverter IV2, the NOA gate NOR1 performs a no operation on the control signal TDCMP and the output of the inverter IV3, and the NAND gate ND2 performs a NAND operation on the control signal TDCMP and the output of the inverter IV2.

The PMOS transistor PM1 is controlled by the output of the NAND gate ND2 to output the power supply voltage level, and the NMOS transistor NM1 is connected in series with the PMOS transistor PM1 and controlled by the output of the NOA gate NOR1 to output the ground voltage level.

In the conventional semiconductor memory device having the above configuration, as shown in FIG. 3, in the normal mode, all banks are sequentially activated according to the bank address signals ATDE <0: 3> to input and output data. However, as shown in FIG. 4, in the test mode, all of the bank address signals ATDE <0: 3> are at a high level to activate all banks, and only the input / output line carrying compressed data among the selected bank data should be tested. The pass fail cannot be determined due to the dummy data of the input / output lines of the bank that are not in the bank. Therefore, there is a problem in that a defect which occurs only in the bank interleave test in the test mode cannot be screened conventionally.

In addition, when all banks are simultaneously activated and tested, all bit line sense amplifiers may be driven at the same time and may be overkill by consuming excessive current.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to fix the data of a bank not selected at the time of data reading in the test mode as data that can always pass through, and to compress the data of the selected bank loaded on the final input / output line. It is possible to determine a low pass failure so that a bank interleave test can be performed.

It also aims at reducing test time by enabling compression testing.

In addition, when all the banks are simultaneously activated and tested, only the bit line sense amplifier for the test mode is driven to prevent the overcurrent, thereby preventing overkill.

According to the present invention for achieving the above object, a plurality of banks which share a global input / output line and are selected and driven by a plurality of bank address signals, and a plurality of banks which amplify data of a selected bank among the plurality of banks in a normal mode Amplifies the input / output sense amplifier for the normal mode and the data of the selected bank among the plurality of banks in the test mode, and is always fixed when data is passed when connected to an unselected bank among the plurality of banks according to the plurality of bank address signals. And a plurality of test mode input / output sense amplifiers for outputting the output signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a configuration diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

The semiconductor memory device includes four banks 100, a plurality of normal mode input / output sense amplifiers 101, a test mode input / output sense amplifier 102, and a plurality of write drivers 103, each bank having a global input / output signal. Share the line GIO (Grobal Input Output).

The semiconductor memory device having the above structure compresses all input / output data of each bank in the test mode, activates one global input / output line GIO, and inputs and outputs data. That is, as shown in FIG. 5, in the case of four banks, 16 data are compressed and output by four by using four global input / output line GIOs. Thus, activating each bank simultaneously compresses all data in each bank, reducing test time to one-quarter without the need for additional address pins.

FIG. 6 is an internal circuit diagram of the input / output sense amplifier 102 for the test mode of FIG. 5.

The input / output sense amplifier 12 for the test mode includes a logic combiner 111, a transfer unit 112, and a driver 113.

The logic combiner 111 logically combines the test mode signal TPARA, the write signal WTS, and the bank address signal ATDE <i> to control the test mode read signal TPARARD, the transfer unit 112, and the drive unit 113. Outputs At this time, the test mode signal TPARA is enabled at the high level in the test mode, the test mode read signal TPARARD is enabled at the high level during the read operation during the test mode, and the write signal WTS is enabled at the high level during the write operation. It is enabled and disabled to the low level during read operation.

To this end, the logic combination unit 111 includes inverters IV4 to IV7, NAND gates ND3, ND4, and NOA gate NOR2.                     

The inverter IV4 inverts the write signal WTS, the NAND gate ND3 NAND-operates the test mode signal TPARA and the outputs of the inverter IV4, and the inverter IV5 inverts the output of the NAND gate ND3 to output the test mode read signal TPARARD. NAND gate ND4 NAND-operates the test mode read signal TPARARD and bank address signal ATDE <i>, inverter IV6 inverts the output of NAND gate ND4, and IV7 inverts the output of inverter IV6. Noah gate NOR2 performs a no operation on the output of inverter IV7 and the compressed data signal TDCMP. At this time, the compressed data signal TDCMP is a data signal output from the bank.

The transfer unit 112 includes an inverter IV8, a PMOS transistor PM2, and an NMOS transistor NM2 and NM3.

The inverter IV8 is controlled by the outputs of the inverters IV6 and IV7 to invert the compressed data signal TDCMP, and the PMOS transistor PM2 and the NMOS transistor NM2 are controlled by the test mode read signal TPARARD to selectively transmit the output of the inverter IV8. NMOS transistor NM3 is connected between NMOS transistor NM2 and the ground voltage terminal and is controlled by the output of inverter IV7.

The driver 113 includes a PMOS transistor PM3 and an NMOS transistor NM4 connected in series between a power supply voltage terminal and a ground voltage terminal, respectively controlled by an output of the transfer unit 112 and an output of the logic combination unit 11. .

As described above, the test mode input / output sense amplifier 102 according to the present invention outputs data as it is if the bank to which the test mode input / output sense amplifier 102 is connected is selected according to the bank address signal ATED <i>. Output fixed high level data.

Hereinafter, a compression test operation during a read operation of the semiconductor memory device of the present invention will be described with reference to FIG. 7.

First, in the compression test mode, when data is input to a data pad (not shown), the input data are multiplexed and transferred as the same input data to the global IO line, and each data is local to the bank and the cell block. It is delivered to a local IO line and written to the cell selected by that address.

Thereafter, upon rewriting the written data, all banks are activated by the bank address signal ATED <0: 3> to drive the input / output sense amplifier 102 for the test mode, and the test mode for the unselected bank. The input / output sense amplifier outputs the output data fixed for the pass to the global input / output line GIO, and outputs the output data of the input / output sense amplifier for the test mode of the selected bank to the global input / output line GIO. The data of the global input / output line GIO is transferred to a compression circuit (not shown), compressed and output, and as a result, the memory cell is tested for defects.

As described above, the present invention can be tested by fixing output data of a non-selected bank as pass data that is always passed, so that it is possible to test whether the output data of the selected bank is normal only with the output data of the selected bank.

Hereinafter, a test operation of the semiconductor memory device will be described with reference to Table 1 and FIG. 7.

TABLE 1

Normal mode Simultaneous driving of 4 banks at the time of lead Right-time four-bank operation Drive only selected bank on read Drive only selected bank at write Unselected bank at lead time Write fertilization bank TPARA L H H H H H H WTS X L H L H L H ATDE <i> X All H All H H X L X GIO Disconnection TDCMP Disconnection TDCMP Disconnection H fixation Disconnection

In Table 1, when the test mode signal TPARA is enabled at the high level, the test mode is entered. When the write signal WTS is enabled at the high level, the test mode is entered into the write mode. When the test mode signal TPARA is enabled at the high level, the test mode signal TPARA is in the read mode. The bank address signal ATED <i> is a signal for selecting a bank, and when enabled at a high level, the bank corresponding to the address is activated. The global input / output line GIO is disconnected by turning off the input / output sense amplifier 102 for the test mode at the time of writing.

As shown in Table 1, when four banks are simultaneously driven during the read operation in the test mode, the compressed data signal TDCMP is loaded on the global input / output line GIO and disconnected during the write operation. At this time, the output data of the unselected bank is fixed to the high level signal, and only the data of the selected bank is compressed to load the compressed data signal TDCMP on the global input / output line GIO. Accordingly, the test is performed only with data of the selected bank.

As shown in Fig. 7, the data of the selected bank is loaded on the global input / output lines GIO <0: 3> only when the compression test mode is read, and the data of the unselected bank is fixed at a high level. Only the actual data can be output for testing.

 As described above, the present invention enables bank interleaving test by fixing the data of the unselected bank to a high level and outputting only the data of the selected bank as the actual data during the read operation of the test mode. It has a reducing effect.

In addition, there is an effect of preventing the transient current in the test mode by driving only the input / output sense amplifiers of the selected bank without driving all of the input / output sense amplifiers at the same time.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (10)

A plurality of banks sharing a global input / output line and selected and driven by the plurality of bank address signals; A plurality of normal mode input / output sense amplifiers for amplifying data of a selected bank among the plurality of banks in a normal mode; And A plurality of banks that amplify data of a selected bank among the plurality of banks in a test mode, and output a fixed output signal with data that is always passed when connected to an unselected bank among the plurality of banks according to the plurality of bank address signals; Input / output sense amplifiers for test mode; A semiconductor memory device comprising a. The method of claim 1, And a plurality of write drivers configured to write data of the global input / output lines to the bank during a write operation. The input and output sense amplifiers of claim 2, A logic combiner for logically combining the write signal activated during the write operation, the bank address signal, and the test mode signal activated during the test mode; A transfer unit controlled by an output of the logical combination unit to transmit a compressed data signal; And A driving unit controlled by an output of the transfer unit and an output of the logical combination unit to output output data to the global input / output line; A semiconductor memory device comprising: a. The method of claim 3, wherein the logical combination portion, A first logic calculator configured to logically operate the test mode signal and the write signal; A second logic operation unit configured to perform a logic operation on the output of the first logic operation unit and the bank address signal; First and second inversion units sequentially inverting the output of the second logic operation unit; And A third logical operation unit configured to perform a logical operation on the compressed data signal and the output of the second inverting unit; A semiconductor memory device comprising: a. The semiconductor memory device of claim 4, wherein the first and second logic operations are NAND gates. 6. The semiconductor memory device of claim 5, wherein the third logic operation unit is a noble gate. The method of claim 4, wherein the delivery unit, A third inverting unit controlled by an output of the first and second inverting units to invert the compressed data signal; First and second switching units controlled by an output of the first logical operation unit to transfer the compressed data signal to the driving unit; And A third switching unit controlled by an output of the second inverting unit and transferring a ground voltage level to the second switching unit; A semiconductor memory device comprising: a. 8. The semiconductor memory device of claim 7, wherein the first switching unit is a PMOS transistor. 8. The semiconductor memory device of claim 7, wherein the second and third switching units are NMOS transistors. The method of claim 7, wherein the driving unit A fourth switching unit controlled by an output of the transfer unit to output a power supply voltage level; And A fifth switching unit controlled by an output of the logic combination unit to output a ground voltage level; A semiconductor memory device comprising: a.

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