KR100744027B1 - Device for controlling test mode - Google Patents

Abstract

TECHNICAL FIELD The present invention relates to a test mode control apparatus, and more particularly, discloses a technique for performing input / output data compression test using one DQ pad. According to the present invention, when no failure occurs in the DRAM cell, the value of each write data output signal and the value of each read data are detected to be equal to each other, and the value of the read data synthesis signal becomes “1”. When a failure occurs in the DQ data controlled by one column selection signal, the value of each write data output signal and the value of each read data are detected differently, and the value of the read data synthesis signal becomes "0". The values of can be written and read independently of each other using the test mode.

Lead data synthesis signal, DRAM, read data, column selection signal, DQ

Description

Device for controlling test mode

1 is a block diagram for controlling a data write operation of the test mode control apparatus according to the present invention.

2 is a configuration diagram for controlling a data read operation of the test mode control apparatus according to the present invention.

3 is a detailed circuit diagram of the logic unit of FIGS. 1 and 2.

4 is a detailed circuit diagram of the multiplexer of FIGS. 1 and 2;

FIG. 5 is a detailed circuit diagram related to the logical operation unit of FIG. 2. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test mode control apparatus, and more particularly, to a technique for performing input / output data compression test using one DQ pad.

In general, with the development of process technology, as semiconductor memory devices are highly integrated, tests are performed for a long time with expensive test equipment after manufacturing to ensure chip reliability. In particular, as the integration density of the DRAM increases, the test time increases, and the cost of the DRAM test increases to increase the capacity of the test equipment.

Therefore, the memory device of the prior art has a self test mode called a data compression test (DQ Compress test) to reduce the test time. The data compression test writes the same data to a plurality of memory cells, reads the data again, compresses the data, and outputs the data. As a result, the memory cells are tested for defects.

As a result, the I / O data compression test mode allows you to test more memory devices at the same time using a single device and to test high-density DRAM without increasing the capacity of your test equipment. It can reduce the share of costs.

Referring to the operation of the conventional input / output data compression test as follows.

First, when data is input to the data pad DQ, this data is input to a circuit multiplexing the input data through the data input buffer. Here, the input data input through the data pad is multiplexed and inputted to the driver and transferred as the same input data to each global IO line, and each data is connected to the bank and the cell block. IO line) and written to the cell selected by address.

Thereafter, when the read data is read again, the data of the cell is amplified by each bit line sense amplifier and transferred to the data compression circuit block through local input / output lines and global lines. Then, it is determined whether the first input data is normally applied to the output terminal, and compresses and outputs a normal state through a logic high or logic low value to the first input data pad. That is, the same data is carried on all the global I / O lines multiplexed from the data pad.

This conventional test mode control device uses four representative DQ pads to compress the DQ data of the DRAM. That is, the DRAM supports multi-bit operations such as x4, x8, and x16, and in the memory cell block, one column select signal Yi controls four DQ data. When the DRAM is tested, the conventional test apparatus uses four DQ pads because the values of the DQ data controlled by one column select signal Yi must be written and read independently of each other.

However, when four DQ pads are used, the number of DRAMs that can be tested simultaneously with one device is limited to one quarter of the channels available on the device. In addition, since the four representative DQ pads must be used in the DRAM supporting the x16 bit configuration as well as the DRAM supporting the x16 bit configuration, the data compression efficiency is deteriorated.

The present invention was created to solve the above problems, and in particular, it is possible to write and read the values of DQ data controlled by one column selection signal independently of each other by using a test mode. Its purpose is to be able to compress DQ data.

The test mode control apparatus of the present invention for achieving the above object, the state of the first write data applied through the first pad, and the first write data group applied through the remaining second pads other than the first pad. First logic means for outputting a plurality of write data compressed signals by logically combining the plurality of inverted signals to be determined; First selecting means for selecting and outputting a first write data, a first write data group or a plurality of write data compressed signals as a plurality of write data output signals according to a state of a compressed signal activated in a test mode; Second logic means for logically combining a plurality of read data stored in a cell with a plurality of inverted signals to output a plurality of read data compressed signals, and for outputting a single read data composite signal by logically combining the plurality of read data compressed signals; And second selecting means for outputting a plurality of read data or one read data composite signal as a plurality of read data output signals according to the state of the compressed signal.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a block diagram of a write control unit for controlling a data write operation of the test mode control apparatus according to the present invention.

The light controller of the present invention includes a plurality of logic units 100, 120, 140, and 160, and a plurality of multiplexers 110, 130, 150, and 170.

Here, the logic unit 100 calculates an exclusive logic sum (XOR2) of the signals of the write data wdata_in0 and the ground voltage VSS level, and outputs the write data compressed signal wdata_comp0. The multiplexer 110 outputs the write data output signal wdata_out0 by multiplexing the write data wdata_in0 and the write data compression signal wdata_comp0 using the compressed signal comp as the selection signal.

The logic unit 120 performs an exclusive logic sum (XOR2) operation on the write data wdata_in0 and the inversion signal reverse1 to output the write data compression signal wdata_comp1. The multiplexer 130 multiplexes the write data wdata_in1 and the write data compression signal wdata_comp1 by using the compressed signal comp as a selection signal and outputs the write data output signal wdata_out1.

The logic unit 140 also performs an exclusive logical sum (XOR2) operation on the write data wdata_in0 and the inversion signal reverse2 to output the write data compression signal wdata_comp2. The multiplexer 150 outputs the write data output signal wdata_out2 by multiplexing the write data wdata_in2 and the write data compression signal wdata_comp2 with the compressed signal comp as the selection signal.

The logic unit 160 calculates an exclusive logic sum (XOR2) of the write data wdata_in0 and the inversion signal reverse3 and outputs the write data compression signal wdata_comp3. The multiplexer 170 multiplexes the write data wdata_in3 and the write data compression signal wdata_comp3 using the compressed signal comp as a selection signal and outputs the write data output signal wdata_out3.

2 is a block diagram of a read controller for controlling a data read operation of the test mode control apparatus according to the present invention.

The read control unit of the present invention includes a plurality of logic units 200 to 230, a logic operation unit 240, and a plurality of multiplexers 250 to 280.

Here, the logic unit 200 calculates an exclusive logic sum (XOR2) of the signals of the read data rdata_in0 and the ground voltage VSS level, and outputs the read data compressed signal rdata_comp0. The logic unit 210 performs an exclusive logical sum (XOR2) operation on the read data rdata_in1 and the reverse signal reverse1 to output the read data compression signal rdata_comp1. In addition, the logic unit 220 performs an exclusive logic sum (XOR2) operation on the read data rdata_in2 and the reverse signal reverse2 to output the read data compressed signal rdata_comp2. The logic unit 230 calculates an exclusive logic sum (XOR2) of the read data rdata_in3 and the reverse signal reverse3 and outputs the read data compressed signal rdata_comp3.

The logical operation unit 240 also performs an exclusive negative logic sum (XNOR4) on the read data compression signals rdata_comp0, rdata_comp1, rdata_comp2, and rdata_comp3 to output the read data synthesis signal rdata_sum.

In addition, the multiplexer 250 multiplexes the read data rdata_in0 and the read data synthesis signal rdata_sum using the compressed signal comp as a selection signal and outputs the read data output signal rdata_out0. The multiplexer 260 multiplexes the read data rdata_in1 and the read data synthesis signal rdata_sum using the compressed signal comp as a selection signal and outputs the read data output signal rdata_out1. The multiplexer 270 multiplexes the signals of the read data rdata_in2 and the ground voltage VSS level using the compressed signal comp as the selection signal, and outputs the read data output signal rdata_out2. The multiplexer 280 multiplexes the signals of the read data rdata_in3 and the ground voltage VSS level using the compressed signal comp as the selection signal, and outputs the read data output signal rdata_out3.

3 is a detailed circuit diagram of the logic unit XOR2 of FIGS. 1 and 2.

The logic unit XOR2 includes a plurality of inverters IV1 to IV3 and a plurality of NAND gates ND1 to ND3. Here, the NAND gate ND1 performs a NAND operation on the input signals in0 and in1 and outputs the result. The NAND gate ND2 performs a NAND operation on the input signal in0 inverted by the inverter IV1 and the input signal in1 inverted by the inverter IV2. The NAND gate ND3 performs a NAND operation on the outputs of the NAND gates ND1 and ND2. The inverter IV3 inverts the output of the NAND gate ND3 and outputs an output signal out.

FIG. 4 is a detailed circuit diagram of the multiplexer 2x1 MUX of FIGS. 1 and 2.

The multiplexer 2x1 MUX includes a plurality of inverters IV4 to IV6 and transmission gates T1 and T2. Here, the transmission gate T1 selectively outputs the input signal in0 according to the state of the control signal s. The transmission gate T2 is complementary to the transmission gate T2 and selectively outputs the input signal in1 according to the state of the control signal s. Inverters IV5 and IV6 non-invert the delay of the outputs of the transfer gates T1 and T2 and output the output signal out.

FIG. 5 is a detailed circuit diagram illustrating the logical operation unit 240 of FIG. 2.

The logic operation unit 240 includes a plurality of inverters IV7 to IV14 and a plurality of NAND gates ND4 to ND10.

Here, the NAND gate ND4 performs a NAND operation on the read data compression signals rdata_comp0 and rdata_comp1. The NAND gate ND5 performs a NAND operation on the read data compression signals rdata_comp2 and rdata_comp3. The NAND gate ND6 performs a NAND operation on the read data compressed signal rdata_comp0 inverted by the inverter IV7 and the read data compressed signal rdata_comp1 inverted by the inverter IV8. The NAND gate ND7 performs a NAND operation on the read data compressed signal rdata_comp2 inverted by the inverter IV9 and the read data compressed signal rdata_comp3 inverted by the inverter IV10.

Inverter IV11 inverts the output of NAND gate ND4. Inverter IV12 inverts the output of NAND gate ND5. Inverter IV13 inverts the output of NAND gate ND6. Inverter IV14 inverts the output of NAND gate ND7. The NAND gate ND8 NAND-operates the outputs of the inverters IV11 and IV12, and the NAND gate ND9 NAND-operates the outputs of the inverters IV13 and IV14. The NAND gate ND10 performs a NAND operation on the outputs of the NAND gates ND9 and ND10 to output the read data synthesis signal rdata_sum.

Referring to the operation of the present invention having such a configuration as follows.

In the present invention, in order to perform a data compression operation using one representative DQ pad, all including a compression signal comp indicating a compression test operation and a reverse signal reverse1 to reverse3 for determining DQ data other than one representative DQ pad. Four test mode signals are required.

First, when data is written to the DRAM without using the compression test mode, the write data wdata_in0 to wdata_in3 input through the DQ pads DQ0 to DQ3 are applied to the logic units 100, 120, 140, 160 and the multiplexers 110, 130, 150, and 170, respectively.

Thereafter, the multiplexers 110, 130, 150, and 170 multiplex the write data wdata_in and the write data compression signal wdata_comp using the compressed signal comp as a selection signal, and output the write data output signal wdata_out. At this time, both the compressed signal comp and the inverted signals reverse1 to reverse3 maintain a "0" state. That is, when the compressed signal comp is "0", the multiplexers 110, 130, 150, and 170 allow the write data wdata_in0 to wdata_in3 to be transmitted to the write data output signals wdata_out0 to wdata_out3, respectively. Subsequently, the write data output signal wdata_out output from the multiplexers 110, 130, 150, and 170 is transferred to and stored in the DRAM cell.

The values of the write data output signal wdata_out stored in the DRAM cell through the logic unit XOR2 of FIG. 3 and the multiplexer (2 × 1 MUX) of FIG. 4 are shown in Table 1 below.

When the data stored in the DRAM is read without using the compression test mode, the read data rdata_in0 to rdata_in3 stored in each cell are applied to the logic units 200 to 230, respectively. The logic operation unit 240 calculates an exclusive negative logic sum (XNOR4) of the read data compression signals rdata_comp0 to rdata_comp3 applied by the logic units 200 to 230, and outputs the read data synthesis signal rdata_sum.

Thereafter, the multiplexers 250 to 280 multiplex the read data rdata_in and the read data synthesis signal rdata_sum using the compressed signal comp as a selection signal, and output the read data output signal rdata_out. That is, the multiplexers 250 to 280 respectively output the read data rdata_in0 to rdata_in3 as the read data output signal rdata_out.

At this time, both the compressed signal comp and the inverted signals reverse1 to reverse3 maintain a "0" state. Subsequently, the read data output signal rdata_out output from the multiplexers 250 to 280 is output to the respective DQ pads.

The values of the read data output signal rdata_out output to the DQ pad through the logic unit XOR2 of FIG. 3 and the multiplexer (2 × 1 MUX) of FIG. 4 are shown in Table 2 below.

Meanwhile, when data is written to the DRAM using the compression test mode, the write data wdata_in0 input through one DQ pad DQ0 is applied to the logic units 100, 120, 140, 160 and the multiplexer 110, respectively. At this time, the write data wdata_in1 to wdata_in3 input through another DQ pad maintains a Don't care state.

Subsequently, each of the logic units 100, 120, 140, and 160 calculates an exclusive logic sum (XOR2) of the write data wdata_in0 and the inverted signals reverse1 to reverse3, respectively, and outputs the write data compression signals wdata_comp0 to wdata_comp3. The multiplexers 110, 130, 150 and 170 multiplex the write data wdata_in0 to wdata_in3 and the write data compression signal wdata_comp using the compressed signal comp as a selection signal and output the write data output signals wdata_out0 to wdata_out3. At this time, the compressed signal comp maintains a "1" state.

That is, when the compressed signal comp is "1", the multiplexers 110, 130, 150, and 170 transmit the write data compression signals wdata_comp0 to wdata_comp3 to the write data output signals wdata_out0 to wdata_out3. Subsequently, the write data output signal wdata_out output from the multiplexers 110, 130, 150, and 170 is transferred to and stored in the DRAM cell.

The values of the write data output signal wdata_out stored in the DRAM cell through the logic unit XOR2 of FIG. 3 and the multiplexer (2 × 1 MUX) of FIG. 4 are shown in Table 3 below.

In addition, when using the compression test mode and reading data stored in the DRAM, read data rdata_in0 to rdata_in3 stored in each cell are applied to the logic units 200 to 230, respectively. Each logic unit 210 to 230 calculates an exclusive logic sum (XOR2) of the read data rdata_in1 to rdata_in3 and the inverted signals reverse1 to reverse3 and outputs the read data compression signals rdata_comp1 to rdata_comp3.

The logic operation unit 240 calculates an exclusive negative logic sum (XNOR4) of the read data compression signals rdata_comp0 to rdata_comp3 applied by the logic units 200 to 230, and outputs the read data synthesis signal rdata_sum.

Thereafter, the multiplexer 250 multiplexes the read data rdata_in0 and the read data synthesis signal rdata_sum using the compressed signal comp as the selection signal and outputs the read data output signal rdata_out0. At this time, the compressed signal comp maintains a "1" state.

That is, when the compressed signal comp is "1", the multiplexer 250 outputs the read data synthesis signal rdata_sum as the read data output signal rdata_out0. The read data output signals rdata_out1 to rdata_out3 are output as signals having a ground voltage level. Subsequently, the read data output signal rdata_out0 output from the multiplexer 250 is output to one DQ pad.

The values of the read data output signal rdata_out output to the DQ pad through the logic unit XOR2 of FIG. 3 and the multiplexer (2 × 1 MUX) of FIG. 4 are shown in Table 4 below.

Therefore, when no failure occurs in the DRAM cell, the value of each write data output signal wdata_out of [Table 3] and the value of each read data rdata_in of [Table 4] are detected to be the same. Then, the value of the read data synthesis signal rdata_sum becomes "1".

On the other hand, when a fail occurs in the DRAM cell, the value of each write data output signal wdata_out of [Table 3] and the value of each read data rdata_in of [Table 4] are detected differently. Then, the value of the read data synthesis signal rdata_sum becomes "0".

As described above, the present invention can perform input / output data compression operation using one DQ pad to simultaneously test four times more DRAMs than four DQ pads, as well as × 8, × 4. It can also be applied to DRAMs that support bit configuration. Accordingly, it is possible to test a large number of DRAM at the same time, thereby reducing the production cost of the DRAM by reducing the proportion of the test cost in the DRAM price.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (14)

Compressing the plurality of write data by logical combination of the first write data applied through the first pad and the plurality of inverted signals for determining the state of the first write data group applied through the remaining second pads other than the first pad. First logic means for outputting a signal; First selecting means for selecting and outputting the first write data, the first write data group or the plurality of write data compressed signals as a plurality of write data output signals according to the state of the compressed signal activated in the test mode; A second logic for logically combining a plurality of read data stored in a cell and the plurality of inverted signals to output a plurality of read data compressed signals, and a second logical logic for combining the plurality of read data compressed signals to output one read data composite signal Way; And And second selection means for outputting the plurality of read data or the one read data composite signal as a plurality of read data output signals in accordance with the state of the compressed signal. The method of claim 1, When a failure does not occur in the cell, the plurality of write data output signals and the plurality of read data are output with the same value, and the value of the one read data composite signal becomes high. And a plurality of write data output signals and a plurality of read data values are different from each other when a failure occurs in the cell, and the value of the one read data synthesis signal is low. The method of claim 1, wherein the first logic means A first logic unit configured to output a first write data compressed signal by performing an exclusive OR operation on the first write data and a first signal having a ground voltage level; A second logic unit configured to perform an exclusive OR operation on the first write data and the first inverted signal to output a second write compressed signal; A third logic unit configured to perform an exclusive OR operation on the first write data and the second inverted signal to output a third write compressed signal; And And a fourth logic unit configured to perform an exclusive-OR operation on the first write data and the third inverted signal to output a fourth write compressed signal. The method of claim 1, wherein the first selection means The first write data and the first write data group are selected as the plurality of write data output signals when the compressed signal is inactivated, and the plurality of write data compressed signals are output when the compressed signal is activated. The test mode control device, characterized in that for selecting and outputting the write data output signal. The method of claim 1, wherein the first selection means A first multiplexer configured to output the first write data output signal by multiplexing the first write data and the first write data compressed signal using the compressed signal as a selection signal; A second multiplexer outputting a second write data output signal by multiplexing the second write data and the second write data compression signal corresponding to the first write data group using the compressed signal as a selection signal; A third multiplexer outputting a third write data output signal by multiplexing the third write data and the third write data compression signal corresponding to the first write data group using the compressed signal as a selection signal; And And a fourth multiplexer for outputting a fourth write data output signal by multiplexing the fourth write data and the fourth write data compression signal corresponding to the first write data group using the compressed signal as a selection signal. Test Mode Control Unit. The method of claim 1, wherein the second logic means A fifth logic unit configured to perform an exclusive OR operation on the second signal having the first lead data and the ground voltage level to output the first read data compressed signal; A sixth logic unit configured to perform an exclusive OR operation on the second lead data and the first inverted signal to output a second read data compressed signal; A seventh logic unit configured to perform an exclusive OR operation on the third lead data and the second inverted signal to output the third lead data compressed signal; An eighth logic unit configured to perform an exclusive OR operation on the fourth lead data and the third inverted signal to output the fourth lead data compressed signal; And And a logical operation unit configured to output the one read data synthesis signal by performing an exclusive negation operation on the first to fourth lead data compressed signals. The method of claim 6, wherein the logical operation unit A first NAND gate NAND-operating the first lead data compressed signal and the second lead data compressed signal; A second NAND gate NAND-operating the third lead data compressed signal and the fourth lead data compressed signal; A third NAND gate NAND-operating an inverted signal of the first lead data compressed signal and an inverted signal of the second lead data compressed signal; A fourth NAND gate NAND-operating the inverted signal of the third lead data compressed signal and the inverted signal of the fourth lead data compressed signal; A fifth NAND gate NAND-operating the inverted signal of the first NAND gate output and the inverted signal of the second NAND gate output; A sixth NAND gate NAND-operating the inverted signal of the third NAND gate output and the inverted signal of the fourth NAND gate output; And And a seventh NAND gate configured to NAND-operate the outputs of the fifth NAND gate and the sixth NAND gate to output the one read data composite signal. The method of claim 1, wherein the second selection means When the compressed signal is inactivated, the plurality of read data are selected and output as the plurality of read data output signals, and when the compressed signal is activated, the one read data composite signal is selected as a first read data output signal. The test mode control device, characterized in that the output to the 1 pad, and the remaining lead data output signal to the ground voltage level. The method of claim 1, wherein the second selection means A fifth multiplexer configured to output a first read data output signal by multiplexing the first read data and the one read data composite signal using the compressed signal as a selection signal; A sixth multiplexer outputting a second read data output signal by multiplexing a second signal having a second read data and a ground voltage level using the compressed signal as a selection signal; A seventh multiplexer outputting a third lead data output signal by multiplexing the third lead data and the second signal using the compressed signal as a selection signal; And And an eighth multiplexer configured to output a fourth read data output signal by multiplexing the fourth read data and the second signal using the compressed signal as a selection signal. The test mode control apparatus of claim 1, wherein the compression signal and the plurality of inverted signals are kept low during the read / write operation of the cell when the cell is not in the test mode. The test mode control apparatus of claim 1, wherein the compressed signal is high when the data is written to the cell in the test mode, and the plurality of inverted signals maintain a money care state. The test mode control apparatus of claim 1, wherein the compressed signal becomes high when data stored in the cell is read in the test mode. The method of claim 1, wherein each of the first logic means and the second logic means An eighth NAND gate NAND-operating the first input signal and the second input signal; A ninth NAND gate NAND operation of the inverted signal of the first input signal and the inverted signal of the second input signal; A tenth NAND gate NAND-operating the outputs of the eighth NAND gate and the ninth NAND gate; And And an inverter for outputting an output signal by inverting the output of the tenth NAND gate. The method of claim 1, wherein each of the first and second selection means A first transmission gate selectively outputting a first input signal according to an activation state of the compressed signal; A second transmission gate operating complementary to the first transmission gate and selectively outputting a second input signal according to an activation state of the compressed signal; And And an inverter chain configured to output an output signal by non-inverting the output of the first transmission gate and the second transmission gate.

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