KR20090066487A - Circuit for data compression testing - Google Patents

Circuit for data compression testing Download PDF

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Publication number
KR20090066487A
KR20090066487A KR1020070134043A KR20070134043A KR20090066487A KR 20090066487 A KR20090066487 A KR 20090066487A KR 1020070134043 A KR1020070134043 A KR 1020070134043A KR 20070134043 A KR20070134043 A KR 20070134043A KR 20090066487 A KR20090066487 A KR 20090066487A
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South Korea
Prior art keywords
data
output
unit
input
signal
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KR1020070134043A
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Korean (ko)
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차재훈
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주식회사 하이닉스반도체
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Priority to KR1020070134043A priority Critical patent/KR20090066487A/en
Publication of KR20090066487A publication Critical patent/KR20090066487A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers

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  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

A data compression test circuit is provided, which improves the test reliability by determining the sameness the read data and the written data in the compression of data test mode. An input unit(50) delivers data to a plurality of write global lines. The write driving part(51) delivers the delivered data to a plurality of corresponding local lines. The memory cell(52) stores the delivered data. The data sensing amplifier part(53) delivers the stored data to a plurality of corresponding test global lines by amplifying it. The compression part(54) outputs the judgment signal by determining the sameness of data delivered through a plurality of test global lines and data delivered through a part among a plurality of write global lines.

Description

Circuit for data compression testing

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuits, and more particularly, to data compression test circuits that perform tests by compressing data to reduce test time.

Recently, semiconductor memory devices have improved data transfer speeds by increasing the number of data pads (DQs) to increase bandwidths. However, if the number of data pads DQ is large, the number of semiconductor memory devices that can be tested at the same time is reduced, thereby increasing test time. To improve this, the semiconductor memory device uses a data compression mode (DQ Compression mode) that reduces the number of data pads (DQ) during the test.

Data compression mode (DQ Compression mode) is a test mode used to test the chip in the wafer state. In a typical data compression mode, the same data is read / written to 16 data pads. That is, the test time and cost can be reduced to 1/16 by performing one read / write process corresponding to 16 identical data.

For example, suppose there are 16 pads of equipment for testing a semiconductor memory device. If the semiconductor memory device to be tested is X16, 16 data pads (DQs) should be read. However, if data compression is performed, the same data at once is performed. Reads and writes to 16 pads, so only one data pad needs to be read. Thus, the time and cost required to test per wafer can be reduced to 1/16.

Since the data compression mode is an operation on the same data, the data compression test circuit includes a data compression test circuit that determines that the 16 data are the same or a fail when the 16 data are not identical.

Referring to FIG. 1, the data compression test circuit according to the related art includes an input unit 10, a write driver 11, a memory cell 12, a data sense amplifier 13, a compressor 14, and an output unit 15. It includes.

Referring to the operation, the input unit 10 transmits the input data DIN <0> to the write global line WGIO <0:15>, and the write driver 11 drives the data loaded on the write global line WGIO <0:15>. Stored to memory cell 12 via local line LIO <0:15>. The data stored in the memory cell 12 is transferred to the data sense amplifier 13 through the local lines LIO <0:15>, and the data sense amplifier 13 transfers the data carried on the local lines LIO <0:15>. It is amplified and delivered to the compression unit 14 through the test global line TGO <0:15>. The compression unit 14 determines whether the data transmitted through the test global line TGO <0:15> are the same and transmits the determination signal TCOM <0> to the output unit 15, and the output unit 15 determines the determination signal. Buffer TCOM <0> and output the output data DOUT <0>.

 Referring to FIG. 2, the compression units 20, 21, and 22 outputting comparison signals COM <0: 3> by comparing four pieces of data transmitted through the test global line TGO <0:15>. And a second comparison unit 24 for comparing the comparison signals COM <0: 4> and outputting the determination signal TCOM <0>.

Referring to FIG. 3, the first comparator 20 outputs a comparison signal COM <0> to logic high when all data transmitted through the test global lines TGO <0: 3> are the same. All of the first comparators 21, 22, and 23 are configured as shown in FIG. 3, and each of the first comparators 21, 22, and 23 receives each comparison signal COM <1: 3> when the input data are the same. Output to logic high.

Referring to FIG. 4, when the comparison signals COM <0: 3> are all input to logic high, that is, when the data transmitted through the test global line TGO <0:15> are all the same, the second comparator is enabled. When the signal EN is applied, the decision signal TCOM <0> is output to logic high.

However, since the data compression test circuit according to the related art determines only whether the data transmitted to the test global line TGO <0:15> is the same, the data written at the same time may be caused due to leakage of the memory cell. There is a problem in that an error determination cannot be made when the data read by the transition is changed from the data written first.

The present invention provides a data compression test circuit for improving test reliability by determining whether the written data and the read data are the same in the data compression test mode.

The present invention also provides the data compression test circuit that minimizes additional area increase and improves test reliability.

The data compression test circuit of the present invention includes an input unit which receives data and latches the data and delivers the data to a plurality of write global lines; A light driver driving the data transmitted through the plurality of write global lines and transferring the data to a corresponding plurality of local lines; A memory cell storing the data transferred to the plurality of local lines; A data sense amplifier unit which receives the data stored in the memory cell through the plurality of local lines, amplifies the data, and transfers the data to a plurality of corresponding test global lines; A compression unit configured to determine whether data transmitted through some of the plurality of write global lines and data transmitted through the plurality of test global lines are the same and output a determination signal; And an output unit for buffering and outputting the determination signal.

The input unit may include an input buffer unit configured to buffer and output the data; An input latch unit configured to output a signal synchronized with an output of the input buffer unit to a rising and falling clock, respectively; A plurality of muxes configured to mux and output a signal synchronized with the rising clock and a signal synchronized with the falling clock by a test signal; And a plurality of input sense amplifiers amplifying and latching outputs of the respective mux units and transferring the latches to the plurality of write global lines.

Each of the input sense amplifiers includes: amplifying units for amplifying and inverting each signal output from the mux unit; And latch units latching a signal driven by an output of each of the amplifiers and transferring the signals to the write global lines.

The compression unit may include: a plurality of first comparison units configured to output the comparison signal by determining whether data transmitted through the at least two test global lines and data transmitted through the write global line are the same; And a second comparator configured to determine whether the comparison signals output from the first comparators are the same and output the determination signal.

Each of the first comparators may include: a first determiner configured to determine whether data transmitted through the at least two test global lines are the same; And a second determiner configured to determine whether the determination result of the first determiner is identical to data transmitted through the write global line and output the comparison signal.

The second comparator may include: a determiner configured to determine whether the comparison signals output from the first comparator are the same; if the comparison signals are the same, pull-up driving is performed by an output of the determiner to output the determination signal having a power voltage level. A pull-up driving unit; And a pull-down driving unit which pulls down the output of the determination unit to output the determination signal having a ground voltage level when the comparison signals are different.

Another data compression test circuit of the present invention includes: a write path unit configured to latch input data and store the plurality of memory cells through a plurality of write global lines; And a read path unit configured to determine whether the input data transmitted through the plurality of global lines and the output data transmitted through the plurality of test global lines from the plurality of memory cells are the same and output a determination signal. .

The write path unit may include an input unit configured to latch the input data and to transfer the input data to the plurality of write global lines; A light driver driving the input data transmitted through the plurality of write global lines and transferring the input data to a corresponding plurality of local lines; And a memory cell storing the input data transferred to the plurality of local lines.

The read path unit may include: a data sense amplifier unit configured to receive and amplify the input data stored in the memory cell through the plurality of local lines and transfer the output data to the plurality of test global lines as the output data; And a compression unit configured to determine whether the input data transmitted through the plurality of global lines and the output data transmitted through the plurality of test global lines are the same and output a determination signal.

The compression unit may include: a plurality of first comparison units configured to determine whether at least two output data and the input data are the same and output a comparison signal; And a second comparator configured to determine whether the comparison signals output from the first comparators are the same and output the determination signal.

The present invention includes a compression unit that compares write data applied through some write global lines with read data applied through the test global line, thereby providing a data compression test circuit for determining whether the write data and the read data are the same. This improves test reliability.

In addition, the present invention focuses on the data being written through the write global line to maintain a latched state, thereby minimizing additional circuit configuration of the compression unit, thereby preventing an increase in area and improving test reliability.

In the data compression test mode, a preferred embodiment of a data compression test circuit for improving test reliability by comparing the written data with the read data and determining the same without additional area increase is shown in FIG. 5.

Referring to FIG. 5, a data compression test circuit according to an exemplary embodiment of the present invention includes an input unit 50, a write driver 51, a memory cell 52, a data sense amplifier 53, a compressor 54, and an output unit. And 55.

Here, the input unit 50, the write driver 51, the memory cell 52, the data sense amplifier 53, and the output unit 55 may include the input unit 10 of the conventional data compression test circuit (FIG. 1), The write driver 11, the memory cell 12, the data sense amplifier 13, and the output unit 15 respectively correspond to each other and have the same configuration and operation.

However, in the data compression test circuit of the present invention, unlike the conventional compression unit 14, the compression unit 54 receives the write data and the test global line TGO received from some write global lines WGIO <0, 4, 8, 12>. It is determined whether the read data input through <0:15> is the same.

Before looking at the compression unit 54, it is necessary to look at the input unit 50 that transfers write data to the write global line WGIO <0:15>. That is, since the input unit 50 latches the write data loaded on the write global line WGIO <0:15> until the next write data is applied, the present invention provides a partial write global line WGIO <0, 4, 8, 12>. By connecting the to the compression unit 54, the write data and the read data can be compared without additional circuit configuration.

Referring to FIG. 6, the input unit 50 includes an input buffer unit 60 that buffers and outputs write data DIN, and an input latch unit which latches the output IN of the input buffer unit 60 by rising and falling clocks RCLK and FCLK. 61, a plurality of input muxes MUX_0, MUX_1, which mux the output of the input latch section 61 by the test signal TM and output four signals ALR <0: 1> and ALF <0: 1>, respectively. MUX_2, MUX_3) and a plurality of input sense amplifiers amplifying the output DINR <0: 1> and DINF <0: 1> of each mux section (MUX_0, MUX_1, MUX_2, MUX_3) and outputting them to four write global lines WGIO, respectively. And SA_0, SA_1, SA_2, and SA_3.

Here, each input sense amplifier SA_0, SA_1, SA_2, SA_3 is configured as shown in FIG. 7. That is, the input sensing amplifier SA_0 includes four amplifiers 70 and four latches 72. The amplifier 70 is controlled by the clock CLK and inverts the signals amplified by the signals DINR <0> and DINRB <0> output from the mux unit MUX_0 to output signals D0 and D0B. The latch unit 72 latches the signals driven by the signals D0 and D0B and applies them to the write global line WGIO <0>.

That is, the signal transmitted to the write global line WGIO <0:15> remains latched until the next write data is input by the input sense amplifiers SA_0, SA_1, SA_2, and SA_3.

As a result, the compression unit 54 may receive write data latched through some write global lines WGIO <0, 4, 8, 12>.

Subsequently, referring to FIG. 8, the compressor 54 compares four read data delivered through the test global line TGO and one write data delivered through the write global line WGIO. The combination of the plurality of first comparison units 80, 81, 82, and 83 outputting the signal COM and the comparison signals COM <0: 3> output from each of the first comparison units 80, 81, 82, and 83 are determined. And a second comparator 84 for outputting the signal TCOM <0>.

Each of the first comparators 80, 81, 82, and 83 may be configured as shown in FIG. 9. Referring to FIG. 9, the first comparison unit 80 may include a first determination unit 92 and a first determination unit that determine whether read data transmitted through four test global lines TGO <0: 3> are the same. And a second determination unit 94 for determining whether the result of the determination in step 92 and the write data transmitted through the write global line WGIO <0> are the same and outputting a comparison signal COM <0>.

The first determination unit 92 includes NAND gates ND1 and ND2 and NOR gates NOR1 and NOR2. Each of the NAND gates ND1 and ND2 is output as logic low when the data of the input test global lines TGO <0: 1> and TGO <2: 3> is logic high, and each of the NOR gates NOR1 and NOR2 is Outputs logic high when the data of the test global lines TGO <0: 1> and TGO <2: 3> that are input is logic low.

The second determination unit 94 includes NAND gates ND3 and ND4, NOR gate NOR3, and inverters IV1 and IV2. The NOR gate NOR3 receives a signal obtained by inverting the outputs of the respective NAND gates ND1 and ND2 and the write data transferred to the write global line WGIO <0> by the inverter IV1. The output of the NOA gates NOR1 and NOR2 and a signal obtained by inverting the write data transmitted to the write global line WGIO <0> by the inverter IV1 are received. The NAND gate ND4 receives a signal inverting the output of the NOR gate NOD3 and an output of the NAND gate ND3, and outputs a comparison signal COM <0> to logic high when any one of them is logic low.

That is, the first comparator 80 compares the signal COM <when the read data transmitted through the four test global lines TGO <0: 3> and the write data transmitted through the write global line WGIO <0> are the same. Output 0> to logic high. Similarly, each of the first comparators 81, 82, 83 outputs a comparison signal COM <1: 3>.

Referring to FIG. 10, the second comparator 84 is configured in the same manner as in the prior art. That is, the determination unit 100 and the comparison signals COM <0: 3>, which determine whether the comparison signals COM <0: 3> output from the first comparison units 80, 81, 82, and 83 are the same, In the same case, the pull-up driving unit 102 for outputting the determination signal TCOM <0> of the power supply voltage level by the pull-up driving by the output of the determination unit 100 and the determination unit 100 when the comparison signals COM <0: 3> are different And a pull-down driving unit 104 which pulls down by the output of the output signal and outputs the determination signal TCOM <0> of the ground voltage level.

The determination unit 100 includes a NAND gate ND5 and an inverter IV3, and all of the comparison signals COM <0: 3> output from the first comparison units 80, 81, 82, and 83 are all logic high. In the same case, the output of the determination unit 100 is output at logic high.

The pull-up driver 102 includes a NAND gate ND6 and a PMOS transistor P1. When the output of the determiner 100 is logic high, the pull-up driver 102 drives the PMOS transistor P1 when the enable signal EN is enabled. Output the decision signal TCOM <0> to logic high.

The pull-down driver 104 includes a NOR gate NOR4 and an NMOS transistor N1. When the inverted enable signal ENb is low enabled when the output of the determiner 100 is logic low, the pull-down driver 104 may turn on the NMOS transistor N1. Drive to output the decision signal TCOM <0> to logic low.

Here, the determination signal TCOM <0> is output through the common drain of the PMOS transistor P1 and the NMOS transistor N1.

In other words, the second comparator 82 includes 16 read data transmitted through the test global line TGO <0:15> and 4 writes transmitted through the write global line WGIO <0, 4, 8, 12>. If the data are all the same, the decision signal TCOM <0> is output to logic high.

Referring to the operation of the data compression test circuit of the present invention, the input unit 50 transfers the input data DIN <0> to the write global line WGIO <0:15>, and writes the write global line WGIO <0 until the next write operation is performed. Latch the write data shown in: 15>.

The write driver 51 drives the data on the write global line WGIO <0:15> and stores the data in the memory cell 52 through the local line LIO <0:15>.

Data stored in the memory cell 52 is transferred to the data sense amplifier 53 through the local lines LIO <0:15>, and the data sense amplifier 53 read data loaded on the local lines LIO <0:15>. Is amplified and transmitted to the compression unit 54 through the test global line TGO <0:15>.

The compression unit 54 determines whether the read data transmitted through the test global line TGO <0:15> and the write data latched through the write global lines WGIO <0, 4, 8, 12> are the same. The signal TCOM <0> is output, and the output unit 55 buffers the determination signal TCOM <0> to output the output data DOUT <0>.

As described above, the data compression test circuit of the present invention minimizes the additional circuit configuration and determines whether the write data and the read data are the same, thereby minimizing the increase of the area and improving the test reliability.

1 is a block diagram showing a data compression test circuit according to the prior art.

2 is a block diagram illustrating a compression unit of FIG. 1.

3 is a detailed circuit diagram of a first comparator of FIG. 2.

4 is a detailed circuit diagram of a second comparator of FIG. 2.

5 is a block diagram illustrating a data compression test circuit in accordance with an embodiment of the present invention.

6 is a block diagram illustrating an input unit of FIG. 5.

FIG. 7 is a detailed circuit diagram of the input sense amplifier of FIG. 6. FIG.

8 is a block diagram illustrating a compression unit of FIG. 5.

FIG. 9 is a detailed circuit diagram of the first comparator of FIG. 8. FIG.

FIG. 10 is a detailed circuit diagram of a second comparator of FIG. 8. FIG.

Claims (10)

An input unit configured to receive data and latch the data to deliver the data to a plurality of write global lines; A light driver driving the data transmitted through the plurality of write global lines and transferring the data to a corresponding plurality of local lines; A memory cell storing the data transferred to the plurality of local lines; A data sense amplifier unit which receives the data stored in the memory cell through the plurality of local lines, amplifies the data, and transfers the data to a plurality of corresponding test global lines; A compression unit configured to determine whether data transmitted through some of the plurality of write global lines and data transmitted through the plurality of test global lines are the same and output a determination signal; And An output unit for buffering and outputting the determination signal; Data compression test circuit comprising a. The method of claim 1, The input unit, An input buffer unit for buffering and outputting the data; An input latch unit configured to output a signal synchronized with an output of the input buffer unit to a rising clock and a falling clock, respectively; A plurality of muxes configured to mux and output a signal synchronized with the rising clock and a signal synchronized with the falling clock by a test signal; A plurality of input sense amplifiers for amplifying and latching outputs of the respective mux units and transferring the latches to the plurality of write global lines; Data compression test circuit comprising a. The method of claim 2, Each input sense amplifier, Amplification units for amplifying and inverting each signal output from the mux unit; And Latch units for latching a signal driven by an output of each of the amplifiers and transferring the signal to the write global line; Data compression test circuit comprising a. The method of claim 1, The compression unit, A plurality of first comparison units configured to determine whether the data transmitted through the at least two test global lines and the data transmitted through the write global line are the same and output the comparison signal; And A second comparator for determining whether the comparison signals output from the first comparators are the same and outputting the determination signal; Data compression test circuit comprising a. The method of claim 4, wherein Each of the first comparison units, A first determining unit determining whether the data transmitted through the at least two test global lines are the same; And A second determination unit which determines whether the determination result of the first determination unit is identical to the data transmitted through the write global line and outputs the comparison signal; Data compression test circuit comprising a. The method of claim 4, wherein The second comparison unit, A determination unit which determines whether the comparison signals output from the first comparison units are the same; A pull-up driving unit configured to output the determination signal of a power supply voltage level by driving the pull-up by the output of the determination unit when the comparison signals are the same; And A pull-down driving unit which pulls down the output of the determination unit to output the determination signal having a ground voltage level when the comparison signals are different; Data compression test circuit comprising a. A write path unit configured to latch input data and store the input data in a plurality of memory cells through a plurality of write global lines; And A read path unit configured to determine whether the input data transmitted through the plurality of global lines and the output data transmitted through the plurality of test global lines from the plurality of memory cells are the same and output a determination signal; Data compression test circuit comprising a. The method of claim 7, wherein The light path unit, An input unit for latching the input data and transferring the input data to the plurality of write global lines; A light driver driving the input data transmitted through the plurality of write global lines and transferring the input data to a corresponding plurality of local lines; And Memory cells for storing the input data delivered to the plurality of local lines; Data compression test circuit comprising a. The method of claim 7, wherein The lead path portion, A data sense amplifier unit for receiving and amplifying the input data stored in the memory cell through the plurality of local lines and transferring the output data to the plurality of test global lines as the output data; And A compression unit configured to determine whether the input data transmitted through the plurality of global lines and the output data transmitted through the plurality of test global lines are identical and output a determination signal; Data compression test circuit comprising a. The method of claim 9, The compression unit, A plurality of first comparison units configured to determine whether at least two output data and the input data are the same and output a comparison signal; And A second comparator for determining whether the comparison signals output from the first comparators are the same and outputting the determination signal; Data compression test circuit comprising a.
KR1020070134043A 2007-12-20 2007-12-20 Circuit for data compression testing KR20090066487A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8867287B2 (en) 2012-05-25 2014-10-21 SK Hynix Inc. Test circuit and method of semiconductor memory apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8867287B2 (en) 2012-05-25 2014-10-21 SK Hynix Inc. Test circuit and method of semiconductor memory apparatus

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