KR100728979B1 - Data path malfunction test circuit for semiconductor memory device - Google Patents

Abstract

A data path malfunction test circuit for a semiconductor memory device capable of comparing test data with data at a position on each path in order to detect a data error on a read path and a write path of the semiconductor memory device is provided to quickly track a malfunction generation path. A register part(10) stores test data provided from the outside for a test. A comparison part(20,30) outputs a malfunction detection signal to judge an error on a corresponding path by comparing the test data stored in the register part with read or write data generated on a read or write path when a read or write operation is performed using the test data. The register part stores CAS latency information regulating time delay by the configuration of a memory internal circuit when a read command is applied from the outside, and burst length information setting the number of data to be read or written from an initially designated address.

Description

DATA PATH MALFUNCTION TEST CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE}

1 is a block diagram of a data path failure test circuit according to an exemplary embodiment of the present invention.

2 is a block diagram illustrating an example in which a data path failure test circuit according to an exemplary embodiment of the present invention is applied to a write or read path of a semiconductor memory device.

The present invention relates to a semiconductor memory device, and more particularly, to a data path failure test circuit of a semiconductor memory device capable of testing a defect occurring in a write and read path.

In general, a semiconductor memory device such as a DRAM writes or reads data through a write path or a read path.

Specifically, in the write path, data input from the outside through the input / output pad is input to the data input register through the data input buffer, latched in the data input register, and then input to the write driver via the input / output bus line.

The data input to the write driver is then transferred to the data bus line when the word line is activated and then stored in the memory cell by the operation of the bit line sense amplifier.

In the read path, when the column select signal, which is an output signal of the column decoder, is enabled, data of the memory cell amplified by the bit line sense amplifier in the row address path is transferred to the data bus line via the bit line.

Then, the data transferred to the data bus line is amplified again by the data bus line sense amplifier and then input into a pipeline structure consisting of a plurality of pipe registers via the input / output bus lines.

Thereafter, the data input in the pipeline structure is latched in the plurality of pipe registers and then output to the outside through the data output buffer activated by the output enable signal and the casbar signal.

As described above, the semiconductor memory device is designed to store data input from the outside in a memory cell through a write path, and output data stored in the memory cell through the write path to the outside.

In addition, when a product comes out after design, an undesired defect may occur when the semiconductor memory device is designed, and when the defect is analyzed, the defect may be reviewed and analyzed in all circuits to track the defect.

However, in the semiconductor memory device including the read path and the write path, since there are countless circuits in each path, there is a problem in that a defective circuit cannot be easily found.

Accordingly, an object of the present invention is to configure a test circuit capable of comparing test data with data at a predetermined position of each path in order to detect data errors in read and write paths of a semiconductor memory device, thereby tracking the path of failure. For sake.

A data path failure test circuit of a semiconductor memory device for achieving the above object includes a register unit for storing test data provided externally for a test; And comparing the test data stored in the register unit with the read or write data generated on the read or write path when the read or write operation is performed with the test data, respectively, and output a defect detection signal for determining an error of the corresponding path. Comparing unit; characterized in that it comprises a.

In the above configuration, the register section sets the cas latency information that defines a time delay by the configuration of the memory internal circuitry when a read command is externally applied, and a burst length that sets how many data to read or write from the first designated address. It is desirable to store the information.

In the above configuration, the comparison unit compares test data stored in the register unit with read data read between a data bus line sense amplifier and a pipeline in the read path, and the test data stored in the register unit and data in the write path. It is desirable to compare the write data written between the input register and the write driver.

In the above configuration, the comparing unit includes: first comparing means for comparing test data stored in the register unit with read data on the read path and outputting the first failure detection signal; And second comparing means for comparing the test data stored in the register unit with the write data on the write path and outputting the second defective detection signal.

In the above configuration, it is preferable that the first comparing means stores burst length information for setting how many data to read or write from the first designated address.

In the above configuration, the second comparing means sets the cas latency information that defines the time delay by the configuration of the memory internal circuit when a read command is applied from the outside, and how many data to read or write from the first designated address. It is preferable to store burst length information.

In the above configuration, it is preferable that the first and second comparison means are independently controlled by receiving different test signals during the test.

In the above configuration, the first and second comparison means are respectively connected with the first and second pads used for the memory operation, and during the test, the first and second failure detection signals are transmitted through the first and second pads. It is preferable to output to the outside.

In the above configuration, the first and second comparing means are connected with third and fourth pads, respectively, which are not used for a memory operation, and during the test, the first and second failures are detected through the third and fourth pads. It is preferable to output the signal to the outside.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As an embodiment of the present invention is shown in the block diagram of Figure 1, an embodiment of the present invention is the test data (TDATA) input from the outside for the test and the read or write data (RDATA, WDATA) transferred to the read or write path By comparing each of them, we test the failure at a specific location of the light or lead path.

Specifically, in the embodiment of FIG. 1, the register unit 10 storing test data TDATA input from the outside, the test data TDATA stored in the register unit 10, and the write data transferred to the memory cell through the write path. The write comparator 20 for comparing the WDATA and outputting it as a write failure detection signal WDETECT, and the test data TDATA stored in the register unit 10 and the read data RDATA output to the outside through the read path. And a read comparator 30 for outputting a read defect detection signal R DETECT.

The register unit 10 stores the test data TDATA that is activated by the test enable signal TM and is externally input during the test, and then stores the stored test data TDATA in the write comparator 20 and the read comparator. Forward to 30.

In this case, the register unit 10 may be configured to configure the memory internal circuit when a read command is applied from the outside to determine a point in time when the stored test data TDATA is transferred to the write comparator 20 and the read comparator 30. Cas Latency information defining the time delay caused by the delay, and Burst Length information that sets how many data to read or write from the first designated address are stored.

The write comparator 20 is activated by the test enable signal TMW for writing the test of the write data, and is transmitted to the memory cell through the write path and the test data TDATA provided from the register unit 10 and the write data WDATA. After comparing the, and when the test data (TDATA) and the write data (WDATA) is matched, outputs the write failure detection signal (WDETECT) of the disabled state, and when the test data (TDATA) and the write data (WDATA) is inconsistent The write failure detection signal WDETECT in the enabled state is output.

In this case, the write data WDATA refers to write data that passes through some circuits in the write path when the test data TDATA is input and transferred to the write path during the test.

In addition, the write comparison unit 20 sets how many data to read or write from the first designated address in order to compare the test data TDATA provided from the register unit 10 with the write data WDATA of the write path. Burst length information is stored.

The read comparison unit 30 is activated by the test enable signal TMR for testing the read data and is transmitted to the test data TDATA provided from the register unit 10 and externally transmitted through the read path. After comparing the, and when the test data (TDATA) and the read data (RDATA) is matched, the read failure detection signal (RDETECT) of the disabled state is output, and the test data (TDATA) and the read data (RDATA) may be inconsistent When the read failure detection signal RDETECT in the enabled state is output.

In this case, the read data RDATA refers to read data passed through some circuits in the read path after the test data TDATA is input and stored in the memory cell during the test operation.

In addition, the read comparison unit 30 sets the number of data to be read or written from the first designated address in order to compare the test data TDATA provided from the register unit 10 with the read data RDATA of the read path. Burst length information is stored.

An embodiment of the present invention having such a configuration is connected to a predetermined position of a write and read path of a semiconductor memory device to detect a failure at each predetermined position. For example, between the data input register 80 and the write driver 90, And an operation of detecting a failure between the bus line sense amplifier 110 and the pipeline 120, respectively, will be described in detail with reference to FIG.

First, the test data TDATA input from the outside through the input / output pad 60 during the write operation is buffered through the data input buffer 70 and transferred to the data input register 80, and latched by the data input register 80. And then provided to the write driver 90.

Thereafter, data input to the write driver 90 is transferred to the data bus line DBL when the word line WL is activated, and then stored in the memory cell 102 by the operation of the bit line sense amplifier 101. do.

In the bad test of the write path for the write operation, the test data TDATA passing through the data input buffer 70 is transferred to the register unit 10, and the write data WDATA passing through the data input register 80 is written. It is transmitted to the comparator 20.

The register unit 10 is activated by the test enable signal TM, stores the test data TDATA passed through the data input buffer 70 and transmits the test data TDATA to the write comparator 20. In operation 20, when the test enable signal TMW is enabled, the write failure detection signal is compared by comparing the test data TDATA stored in the register unit 10 with the write data 20 latched by the data input register 80. Outputs (WDETECT).

Thereafter, the write failure detection signal WDETECT is output to the outside through the pad 40, and when the output write failure detection signal WDETECT is in the enabled state, the data input buffer 70 and the data input register 80 are used. It can be seen that a failure occurred between).

In this case, the embodiment of the present invention uses any one of the pads used for the operation of the semiconductor memory device as the pad 40 for transmitting the write failure detection signal WDETECT to the outside, or is not used for the operation of the semiconductor memory device. Any of the pads may be used.

Next, the read data RDATA stored in the memory cell during the read operation is amplified by the bit line sense amplifier 101 when the column select signal YI, which is an output signal of the column decoder, is amplified by the data bus line DBL. Is passed to.

Thereafter, the read data RDATA transferred to the data bus line DBL is amplified by the data bus line sense amplifier 110 when the word line WL is activated, and then the pipeline 120 composed of a plurality of pipe registers. Is passed).

Thereafter, the data input to the pipeline 120 is latched by the plurality of pipe registers and then output to the input / output pad 60 through the data output buffer 130.

In the bad test of the read path for such a read operation, the test data TDATA and the data bus line sense amplifier stored in the register unit 10 are read through the read comparison unit 30 activated by the test enable signal TMR. After comparing the data amplified by 110, a read failure detection signal RDTET is output.

Thereafter, the read failure detection signal R DETECT is output to the outside through the pad 50, and when the read failure detection signal R DETECT output to the outside is in an enabled state, the bus line sense amplifier 110 and the pipeline structure ( It can be seen that a failure occurred between 120).

At this time, the embodiment of the present invention uses any one of the pads used in the operation of the semiconductor memory device as the pad 50 for transmitting the read failure detection signal RDTET to the outside, or is not used in the operation of the semiconductor memory device. Any of the pads may be used.

As described above, the embodiment of the present invention compares the test data TDATA passed through the data input buffer 70 with the write data WDATA at a predetermined position in order to detect a defect at a predetermined position in the write path during the test. And output as a write failure detection signal WDETECT.

In addition, an embodiment of the present invention compares the test data TDATA passed through the data input buffer 70 with the read data RDATA at a predetermined position in order to detect a failure at a predetermined position in the read path during the test. Output as signal RDETECT.

Then, the embodiment of the present invention outputs the write failure detection signal WDETECT and the read failure detection signal RDETECT to the outside through the pads 40 and 50, respectively, and the write failure detection signal WDETECT and read failure It may be determined whether a failure occurs at a predetermined position according to the state of the detection signal RDTET.

Therefore, the present invention can determine whether the circuits connected to the predetermined position is defective by selecting a predetermined position in the write path or the read path during the test, and then comparing the write or read data of the selected position with the test data TDATA. .

In addition, the present invention is a range of a circuit capable of failure test by changing the position in the light path and the lead path, or by connecting a plurality of light comparator 20 and the lead comparator 30 to the light path and the lead path, respectively By narrowing down, we can quickly find the path of failure.

As described above, the present invention selects a predetermined position from each of the write or read paths during the test, and compares the write or read data of the selected location with the test data, respectively, thereby making it possible to easily find the path of failure.

In addition, the present invention is a range of a circuit capable of a failure test by changing the position in the light path and the lead path, or by connecting a plurality of light comparator 20 and the lead comparator 30 to the light path and the lead path, respectively By narrowing, there is an effect that can quickly find the path of failure.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (9)

A register unit for storing test data provided externally for a test; And When performing a read or write operation with the test data stored in the register unit and the test data, the read or write data generated on the read or write path may be compared to output a defect detection signal for determining an error of the corresponding path. Comparing unit; Data path failure test circuit of a semiconductor memory device comprising a. The method of claim 1, The register unit stores cas latency information that defines a time delay caused by the configuration of a memory internal circuit when a read command is externally applied, and burst length information that sets how many data to read or write from the first designated address. A data path failure test circuit of a semiconductor memory device. The method of claim 1, The comparison unit compares the test data stored in the register unit with the read data read between the data bus line sense amplifier and the pipeline in the read path, and the test data stored in the register unit and the data input register and write in the write path. A data path failure test circuit of a semiconductor memory device, characterized by comparing write data written between drivers. The method of claim 1, The comparison unit, First comparing means for comparing the test data stored in the register unit with the read data on the read path and outputting the first defective detection signal; And And second comparing means for comparing the test data stored in the register unit with the write data on the write path to output a second fail detection signal. The method of claim 4, wherein And the first comparing means stores burst length information for setting how many data to read or write from the first designated address. The method of claim 4, wherein The second comparing means includes the cas latency information that defines a time delay caused by the configuration of a memory internal circuit when a read command is applied externally, and burst length information that sets how many data to read or write from the first designated address. And a data path failure test circuit of the semiconductor memory device. The method of claim 4, wherein And the first and second comparison means are independently controlled by receiving different test signals during a test. The method of claim 4, wherein The first and second comparison means are respectively connected to the first and second pads used in the memory operation, and output the first and second failure detection signals to the outside through the first and second pads during the test. And a data path failure test circuit of a semiconductor memory device. The method of claim 4, wherein The first and second comparison means are connected to third and fourth pads, respectively, which are not used for memory operation, and output the first and second failure detection signals to the outside through the third and fourth pads during the test. And a data path failure test circuit of the semiconductor memory device.

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