JPH0583093A - Signal reception circuit - Google Patents

Abstract

PURPOSE:To obtain the signal reception circuit in which the effect of chattering or ringing in a long consecutive time is completely eliminated even when the chattering or ringing for a long consecutive time is included in an inputted digital signal. CONSTITUTION:The intermediate signal C of an EXOR 1 rises by the first leading of an input signal A from an input terminal 53 and a pulse signal D in a prescribed time constant is generated from a monostable multivibrator OS2. A delay signal B is obtained from a TFF 3 with the trailing of a pulse signal D and returned to the other terminal of an EXOR 1 and the intermediate signal C falls down. The operation is similarly implemented even in the case of a trailing of the input signal A. On the other hand, the delay signal B is latched by a DFF 4 at the leading of a pulse signal (d) and the result is led to an output terminal 54 as an output signal E in phase to the input signal A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal receiving circuit, and more particularly to a signal receiving circuit capable of stably receiving a digital signal including chattering or ringing which has a long duration.

[0002]

2. Description of the Related Art In a conventional signal receiving circuit for receiving a digital signal including chattering and ringing, a signal receiving circuit main body 51 is provided at an input portion of a logic element IC 52, as shown in FIG. The signal receiving circuit main body 51 is configured to remove chattering and ringing by using a low-pass filter circuit composed of a capacitor C and a resistor R, and input the chattering and ringing to a logic element IC 52 connected in a subsequent stage. There is.

[0003]

The above-described conventional signal receiving circuit cannot completely eliminate the influence when receiving a digital signal containing chattering or ringing having a long duration, and therefore is connected to the subsequent stage. There is a drawback that the logic element IC to be processed often malfunctions.

It is an object of the present invention to provide a signal receiving circuit by a digital circuit which can completely eliminate the influence even when receiving a digital signal including chattering or ringing having a long duration.

[0005]

According to the signal receiving circuit of the present invention, an exclusive OR circuit having one terminal as a receiving input terminal, a monostable multivibrator circuit and a T-type flip-flop circuit are connected in series. The output signal of the T-type flip-flop circuit is fed back to the other input terminal of the exclusive OR circuit, and the output signal of the T-type flip-flop circuit is latched via the output signal of the monostable multivibrator circuit. A D-type flip-flop circuit is connected.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart of signals for explaining the present embodiment.

The embodiment shown in FIG. 1 has a digital signal input terminal 53, an exclusive OR circuit (hereinafter referred to as EXOR) 1, a monostable multivibrator circuit (hereinafter referred to as OS) 2, and T.
Type flip-flop circuit (hereinafter referred to as TFF) 3, D-type flip-flop circuit (hereinafter referred to as DFF) 4, and digital signal output terminal 54.

Next, the operation of this embodiment will be described with reference to FIG.

Chattering or ringing at the rising edge of the input signal A including chattering or ringing input from the input terminal 53 is indicated by a path E in FIG.
The intermediate signal c of XOR1 also rises including chattering or ringing. Next, the pulse signal D having a constant time constant set in OS2 rises as indicated by a path 11 in FIG. The pulse width T of the pulse signal D is obtained by the time constant preset in OS2. At this time,
In order to prevent the influence of chattering or ringing on the pulse signal D, the pulse width T of the time constant preset in the OS2 needs to be longer than the chattering or ringing duration t. The pulse signal D is input to the TFF 3 via the path 12 in FIG. 2 and becomes the delayed signal B divided in half, returned to the other terminal of the EXOR 1 and the intermediate signal C rises in the path 13 in FIG. Go down.

On the other hand, the delayed signal B is D on the path 14 of FIG.
It is latched by the FF4, its polarity is inverted, and it becomes the output signal E in phase with the input signal A and is guided to the output terminal 54. Also in the case of the fall of the input signal A, the operation is performed by the procedure of the paths 15, 16, 17, 18, and 19 in FIG. Therefore, the rising and falling timings of the output signal E coincide with the corresponding rising and falling timings of the input signal A,
Moreover, it can be seen that the influence of chattering and ringing included in the input signal A is removed.

[0011]

As described above, according to the present invention, the exclusive OR circuit, the monostable multivibrator circuit, and the T-type flip-flop circuit are connected in series, and one input terminal of the exclusive OR circuit is connected. A digital signal is input, the output signal of the T-type flip-flop circuit is fed back to the other input terminal, and the output signal of the T-type flip-flop circuit is latched via the output signal of the monostable multivibrator circuit. By connecting the flip-flop circuit, it is possible to completely eliminate the influence of chattering or ringing of a duration t shorter than the pulse width T of the time constant preset in OS2.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a signal timing diagram illustrating the embodiment.

FIG. 3 is a circuit diagram of a conventional signal receiving circuit.

[Explanation of symbols]

 1 Exclusive-OR circuit 2 Monostable multivibrator 3 T-type flip-flop 4 D-type flip-flop 53 Input terminal 54 Output terminal

Claims (2)

[Claims] 1. An exclusive OR circuit having one terminal as a reception input terminal, a monostable multivibrator circuit, and a T-type flip-flop circuit are connected in series, and the other input terminal of the exclusive OR circuit. The output signal of the T-type flip-flop circuit is fed back to the D-type flip-flop circuit for latching the output signal of the T-type flip-flop circuit via the output signal of the monostable multivibrator circuit. Characteristic signal receiving circuit. 2. The signal according to claim 1, wherein a pulse width of a time constant preset in the monostable multivibrator is set longer than a time constant of chattering or ringing mixed in a reception input. Receiver circuit.