JPH024535Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for determining the sign of a signal that does not use an error correction code in a digital transmission system in which error signals are mixed.

The signal targeted by the present invention is a signal represented by specific bits in a system for transmitting digital signals in units of frames. In particular, this bit is used to perform error control by repeatedly sending the same signal every frame. For example, a satellite broadcast audio signal is a digital signal with one frame consisting of 2048 bits, and this signal is transmitted 1000 times per second. In the frame structure, the first 16-bit code is a frame synchronization signal to facilitate bit clock reproduction on the receiving side, and the next 16-bit code is a control code that indicates the transmitting mode.
A 1-bit or 2-bit code is assigned depending on the control contents, such as the distinction between A and B modes, the distinction between television audio and independent audio, and the distinction between stereo and monaural. This control code is a clock pulse at a frame interval synchronized with each code, and by latching, it appears as a signal with a constant code of "1" or "0" over many frames unless there is a disturbance. However, if there is a disturbance, an error pulse will appear in this signal, so the sign is determined by majority decision. Disturbances cannot be avoided in the radio wave propagation path of the received signal from the broadcasting satellite, and the signal latched frame by frame has a waveform as shown in Figure 1a. This waveform is the original signal shown in FIG. 1b subjected to a positive error pulse e and a negative error pulse e', and this original signal must be determined. If there is only one signal input, the signal can be set to a constant threshold voltage by feeding it to a comparator through a simple integrating circuit as shown in Figure 2a.
The presence or absence of a signal can be determined by obtaining an output only when V _th is exceeded. Figure 2b shows the output waveform of the integrating circuit, and depending on the selection of the time constant CR, e,
The amplitude of the signal wave due to the error pulse e′ does not reach the threshold voltage V _th . Therefore, the output of the comparator shown in FIG. 2c becomes the judgment output. This determination circuit using an analog circuit has a problem when there is not just one digital transmission system but a plurality of digital transmission systems. The control signals of broadcasting satellites are a system that repeatedly transmits signal pulse trains containing various control signals, and these signals are received and arranged in parallel signal lines so that control signals are transmitted to each signal line. Make it. Therefore, since the number of signal lines increases, the aforementioned determination circuit using an analog circuit requires a large number of CRs and comparators. To integrate this circuit, CR
must be an external component, and it is difficult to fully integrate it on a single chip. Furthermore, depending on the occurrence of error signals on the signal line, it is necessary to make the time constant CR variable, which requires the use of a variable capacitor in the above-mentioned circuit.

The purpose of the present invention is to provide a sign determination circuit that eliminates the above-mentioned drawbacks, performs sign determination using a digital method that is easy to integrate, and can appropriately vary the value corresponding to the time constant CR of an analog circuit. It's about doing.

The code determination circuit according to the present invention is arranged at a specific position within one frame, and detects the "1" of the signal in a determination period consisting of a plurality of frames, which is a coded signal that is repeatedly sent in succession for each frame. Or, a determination circuit that determines the sign of the signal by majority decision based on the number of frames in which the signal is "0", and inputs a clock pulse with a frame interval synchronized with the signal, and distinguishes between frames in which the signal is "1" and " 0”
means for dividing the clock pulses between each frame and counting the difference, and outputting the result of adding the clock pulses to an initial count set at the start point of the determination period determined by the frequency-divided pulse of the clock pulse; Verifies each of the two limit count values set above and below the initial count value set above, and outputs "1" when the limit count value is exceeded, and output "0" when it does not exceed the limit count value. At the end of the determination period determined by the two comparison circuits and the frequency division pulse of the clock pulse, when the output of at least one of the comparison circuits is "1", inputting the frequency division pulse as a latch clock of the latch circuit; and latching means for latching one output of the comparison circuit and outputting the determined sign. Then, when the count number does not exceed the upper and lower limit count numbers and the outputs of the two comparison circuits are both "0", a pre-hold characteristic is provided that outputs the code latched in the previous judgment period as the judgment code. I'm leaning on it.

Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 3 is a circuit block diagram of an embodiment of the present invention, and FIG. 4 is a timing chart of each part.
The signals (frame data) input from terminal a for each frame include a frame synchronization signal first, and then a control code. A circuit (not shown) detects this frame synchronization signal, generates the clock pulse shown in FIG. 4B in synchronization with this synchronization signal, and inputs it from the b terminal. Therefore, the interval between clock pulses becomes the frame interval. Then, the clock pulse is delayed by D1 time in a delay circuit ₁₁ in accordance with the bit position of the control code, the input signal is sampled, and is latched to a D-type flip-flop 12 and output. The output 12a of this D-type flip-flop 12 is the signal shown in FIG. 4C.

The clock selection circuit 2 receives the clock pulse from the b terminal and the output signal 1 of the D-type flip-flop 12.
2a is input, and a clock pulse is selected and outputted to the two output terminals as shown in FIG. 4D according to the output signal 12a. The two outputs are respectively led to an up input terminal and a down input terminal of an up-down counter (hereinafter referred to as counter) 3 at the next stage as an up input clock and a down input clock. Here, the clock pulse is signal 1.
It is assumed that the signal is led to the up input terminal during the period when 2a is "1", and to the down input terminal during the period when 2a is "0". On the other hand, the clock pulse is frequency-divided by N by frequency divider 1. Therefore, this frequency divider 1 outputs one pulse for every N clock pulses, which determines the start and end points of the sign determination period. This pulse is sent to the first and second delay circuits 9 and 10, respectively. The first delay circuit 9 outputs a pulse P as shown in FIG. 4A, which is delayed by _D1 time from the rising edge of the clock pulse in order to match this pulse with the rising edge of the signal 12a. This pulse P sets the initial value of the counter 3. Therefore, the counter 3 starts counting every N clock pulses, and this count value output is sent to first and second magnitude comparators (hereinafter referred to as comparators) 4-1 and 4-2.
It will be compared with the comparison numbers provided here. First,
In the second comparators 4-1 and 4-2, upper and lower limit count values N _M and N _L , which are limit count numbers, are set in advance as comparison values. The initial setting value N〓 of the counter 3 mentioned above is also set in advance to satisfy the relationship _NL <N〓< _NM .
The first comparator 4-1 has an input count value _N
When _NX > _NM , the second comparator 4-2 outputs "1", and when the input count value _NX satisfies _NX < _NL , the second comparator 4-2 outputs "1". Here, the pulse output from the frequency divider 1 passes through the second delay circuit 10 and is sent to the judgment output circuit 8 consisting of an OR circuit 5, an AND circuit 6, and a latch circuit 7 as a data latch pulse as shown in FIG. 4G. given as Q. The judgment output circuit 8 uses this data latch pulse Q to take in the output of the first comparator 4-1 as data every N division of the clock pulse. The data latch pulse Q is the pulse from the frequency divider 1 by the second delay circuit 10.
D Pulse delayed by ₂ hours. This D ₂ hours is for capturing the latched data, and D ₁
Since there is no point in matching the bit position of the control code like time, it can be set shorter than _D1 time.
The control operation shown in FIG. 3 will be explained below with reference to FIG. 4 in the case where a control code having a code value of "0" is used for majority decision in 28 frames. In the figure, 28 clock pulses are input from the b terminal as shown at B during the sign determination period determined by the pulse interval every N frequency division (N=28) output from the frequency divider 1. Note that the output of the frequency divider is normally a square wave, but in this circuit, a pulse is output at the rise of the square wave. On the other hand, there is an error in the control code in the input signal from the a terminal, and a positive error pulse is generated in the signal 12a shown in FIG. 4C. Therefore, the clock pulse is sent to the up input terminal and down input terminal of the counter 3 through the clock selection circuit 2, respectively.
The information is divided and input as shown in Figure D. As a result, the contents of counter 3 change from the initial setting value N〓 to the fourth value.
It is counted and changed as shown in Figure E. If this count value exceeds the upper limit N _M or the lower limit N _L , the first comparator 4-1 or the second comparator 4-
2 outputs “1”. In this example, the lower limit N _L is exceeded twice, so the second comparator 4-2
It emits an output pulse as shown in Figure F. Both output pulses of the first and second comparators 4-1 and 4-2 are
is led to the AND circuit 6 via the OR circuit 5, and this
Opens and closes the gate of AND circuit 6. Therefore,
The AND circuit 6 includes first and second comparators 4-1,
The data latch pulse Q of the latch circuit 7 is controlled by either or both of 4-2. In this example, the gate of the AND circuit 6 is opened by the output of the second comparator 4-2. Here, when the data latch pulse Q is sent to the AND circuit 6, the output of the first comparator 4-1 is "0", so the latch circuit 7 takes in the "0" value. In this way, the judgment output circuit 8 outputs the result of the majority judgment in the judgment period to the next N
During the next determination period up to the divided pulse Q, the result of the "0" determination is output. Furthermore, when _the content _N
If N _X <N _M , the first and second comparators 4-
Since the outputs of both frames 1 and 4-2 are "0", the latch circuit 7 holds the same value as the previous frame output.

As can be seen from the above operation, even if there is a positive error pulse, if the period of the positive error pulse within this judgment period is short, the count number will exceed the upper limit N _M at the time the data latch pulse Q is generated. Since there is no such flag, a correct determination of "0" is made. In this example, counter 3
The initial setting value N〓 is set to 28, and the upper limit _NM and lower limit _NL are set so that _NM −N〓 and N〓− _NL become 12, respectively. N _M −N〓, N〓−N _L play the same role as the time constant of the conventional analog system determination circuit, and the initial setting value N〓 corresponds to the threshold value of the analog system comparator. However, a width is provided above and below the threshold value, and this range is used as a dead zone. Note that the maximum count number of the counter 3 within the determination period is set to be 28±28 or more.

As explained above, the sign determination circuit according to the present invention does not require an external CR and has a circuit configuration suitable for integration into an integrated circuit. Furthermore, since the error pulse period is determined by counting the clock pulses,
The initial setting value of the up-down counter and the comparison value of the magnitude comparator can be appropriately determined according to the error characteristics of the error pulse. Also, if the value is within the comparison value of the magnitude comparator, the sign is not checked and the result of the previous judgment period is held until the next judgment period, so it is important to select the threshold width appropriately. Highly reliable sign determination can be performed.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of a signal waveform of a digital transmission system, Fig. 2 is a diagram explaining signal judgment by a conventional signal judgment circuit, Fig. 3 is a circuit block diagram of an embodiment of the present invention, and Fig. 4 is a time chart illustrating the operation of the circuit shown in FIG. 1... Frequency divider, 2... Clock selection circuit, 3...
...(up-down) counter, 4-1, 4-2...
…(magnitude) comparator, 5……OR
Circuit, 6...AND circuit, 7...Latch circuit, 8
. . . Judgment output circuit, 9, 10, 11 . . . Delay circuit, 12 . . . D-type flip-flop.

Claims (1)

[Claims for Utility Model Registration] An encoded signal that is placed at a specific position within one frame and is continuously and repeatedly sent for each frame is determined to be "1" of the signal during a determination period consisting of a plurality of frames. or a determination circuit that determines the sign of the signal by majority decision based on the number of frames in which the signal is "0", and inputs a clock pulse with a frame interval synchronized with the signal, and distinguishes between frames in which the signal is "1" and " means for dividing the clock pulses into frames with a frequency of 0'' and counting the difference, and outputting the result of adding the result to an initial count set at the start point of the determination period determined by the frequency-divided pulse of the clock pulse; Verify the count number against each of the two limit count values set above and below the initial count value set above, and output "1" when the limit count value is exceeded, and output "0" when it does not exceed the limit count value. Two comparison circuits,
At the end of the determination period determined by the frequency division pulse of the clock pulse, when at least one output of the comparison circuit is "1", the frequency division pulse is input as the latch clock of the latch circuit, and one of the comparison circuits latching means for latching the output and outputting the judged code; and a pre-hold characteristic for outputting the code latched in the previous judgment period as the judged code if the upper and lower limit counts are not exceeded. A sign determination circuit comprising: