JPS59174759U

JPS59174759U - Sign determination circuit

Info

Publication number: JPS59174759U
Application number: JP1983068626U
Authority: JP
Inventors: 行弘岡田
Original assignee: 日本電気ホームエレクトロニクス株式会社
Priority date: 1983-05-10
Filing date: 1983-05-10
Publication date: 1984-11-21
Also published as: JPH024535Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図はデジタル伝送系の信号波形例を示す図、第２図
は従来の信号判定回路による信号判定を説明する図、第
３図は本考案の一実施例の回路ブロック図、第４図は第
３図の回路の動作を説明するタイムチャートである。１・・・分周器、２・・・クロック選択回路、３・・・
（アップダウン）カウンタ、４−１．　４−２・・・（
マグニチュード）コンパレータ、５・・・ＯＲ回路、６
・・・ＡＮＤ回路、７・・・ラッチ回路、８・・・判定
出力回路、９．１０・・・遅延回路、ａ・・・信号入力
端子、ｂ・・・クロックパルス入力端子、Ｐ・・・Ｎ分
周パルス、Ｑ・・・データラッチパルス。Fig. 1 is a diagram showing an example of a signal waveform of a digital transmission system, Fig. 2 is a diagram explaining signal judgment by a conventional signal judgment circuit, Fig. 3 is a circuit block diagram of an embodiment of the present invention, and Fig. 4 3 is a time chart illustrating the operation of the circuit shown in FIG. 3. FIG. 1... Frequency divider, 2... Clock selection circuit, 3...
(up-down) counter, 4-1. 4-2...(
magnitude) comparator, 5...OR circuit, 6
...AND circuit, 7...Latch circuit, 8...Judgment output circuit, 9.10...Delay circuit, a...Signal input terminal, b...Clock pulse input terminal, P...・N frequency division pulse, Q...data latch pulse.

Claims

[Scope of utility model registration request]

In a digital transmission system in which an error signal of opposite polarity is mixed into the original signal that is continuously transmitted in units of one frame during transmission, the signal of the transmission system is input, and the one frame period is Prepare clock pulses for time division in advance, and count the difference between the number of clock pulses corresponding to the period when the input signal is °"1" and the number of clock pulses corresponding to the period when the input signal is "°0" within the period. and a means for adding and outputting the count number set at the beginning of the period, and a "1" or "0" pulse respectively when the output count number exceeds the limit count number set above and below the set count number. and a determination output means for detecting and latching the output pulse every frame period.